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Abstract. This paper demonstrates electrical degradation due to Hot Carrier Injection (HCI) stress for nLDMOS devices with different Large Angle Tilted Implantation Doping (LATID) techniques for p-body. It seems that optimization of the device with LATID angle for p-body in nLDMOS is important to achieve improved HCI performance and observed that HCI degradation is minimum for 30 0 LATID for p-body. We observed Si/SiO2 interface trap under various stress conditions, were evaluation based on our Sentaurus simulation, and we compare trapped charge density and distribution for various LATID angles and it was less for 30 0 tilt. Trap-related models were employed to perform Ron and Id,sat degradations during the HCI stress test. So nLDMOS device with 30 0 tilt angle for p-body shows better HCI performance compared to other LATID. Also our new proposed device structure shows less HCI degradations when compared with silicon data of HCI degradations for other nLDMOS structure.

High performance power device is necessary for BCD power device. In this paper, we used 3D Synopsis TCAD simulation tool Sentaurus to develop 120V device and successfully simulated. We implemented in a conventional 0.35um BCDMOS process to present of a novel high side 120V LDMOS have reduced surface field (RESURF) and Liner p-top structure with side isolation technology. The device has been research to achieve a benchmark specific on-resistance of 189 mΩ-mm2 while maintaining horizontal breakdown voltage and vertical isolation voltage both to target breakdown voltage of 120V. In ESOA, we also proposed a better performance of both device without kirk effect.

We used TCAD Synopsys 3D tools and device simulators to propose an innovative device structure of 80V-100V high-side NLDMOS by using the silicon to silicon-di-oxide ratio with side trench. The high-side can also be developed by placing an NBL structure which can deliver a high as over 200V isolation voltage. The 3D structure can clear see the optimized linear p-top and n-drift region have better charge balance with linear doping profile to get the benchmark breakdown voltage (BVdss) of 80V with on-resistance (Ron) as low as 130 mΩ-mm2 and 100V with on-resistance as low as 175 mΩ-mm2.The linear p-type buried layer using high dosage and lower energy to achieve the better SOA and higher isolation voltage. Optimized linear p-top and PBL can improve Ron by 32.5% compare to other 100V high side device which have done from reference.

Abstract. An ESOA of LDMOS device is very critical for power device performance. Kirk effect is the one of the major problem which leads to poor ESOA performance. The cause of the problem mainly due to the high beta value of parasitic NPN transistor in the p-body. In this study, we proposed a new 3D high side SideIsolated N-Channel LDMOS which we have obtained not only benchmark Ron and breakdown performance, but also better ESOA without Kirk effect. We have compared the analysis of Kirk effect between the new device and the conventional N-LDMOS structure with LATID technique for the formation of the p-body of both device structures.