In this letter, microwave annealing over a wide range of power (300–2700 W) in nitrogen ambient was performed on TiN/Al/TiN/HfO2/Si metal-oxide-semiconductor capacitors. Capacitors with rapid thermal annealing at 500 °C were also fabricated for comparison at the same wafer temperature measured during microwave annealing at 2700 W. For microwave annealed capacitors, key parameters such as equivalent oxide thickness, interface state density, oxide trapped charge, leakage current density, and breakdown voltage were all improved with increasing microwave annealing power. For the capacitor with rapid thermal annealing at 500 °C, diffusion of Al into TiN and growth of the interfacial oxide layer are detected, leading to the shift in flat-band voltage and increase in equivalent oxide thickness, respectively. The results further indicate that it is more effective to remove the charged traps by microwave annealing than by rapid thermal annealing, and the reduction in leakage current density after microwave annealing corresponds to the reduction in charge traps based on a trap-assisted tunneling model. With no trade-off relationship between the electrical characteristics and no undesired effect such as diffusion of species, microwave annealing demonstrates great potential for the post-metallization annealing process for the high-k/metal gate structure.

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In this letter, high-temperature ion implantation and low-temperature microwave annealing were employed to achieve high n-type active concentrations, approaching the solid solubility limit, in germanium. To use the characteristics of microwave annealing more effectively, a two-step microwave annealing process was employed. In the first annealing step, a high-power (1200 W; 425 °C) microwave was used to achieve solid-state epitaxial regrowth and to enhance microwave absorption. In the second annealing step, contrary to the usual process of thermal annealing with higher temperature, a lower-power (900 W; 375 °C) microwave process was used to achieve a low sheet resistance, 78Ω/◻, and a high carrier concentration, 1.025 × 1020 P/cm3, which is close to the solid solubility limit of 2 × 1020 P/cm3.

In this study, TiN/HfO2/Si metal-oxide-semiconductor (MOS) capacitors were etched by a neutral beam etching technique under two contrasting conditions. The configurations of neutral beam etching technique were specially designed to demonstrate a “damage-free” condition or to approximate “reactive-ion-etching-like” conditions to verify the effect of plasma-induced damage on electrical characteristics of MOS capacitors. The results show that by neutral beam etching (NBE), the interface state density (Dit) and the oxide trapped charge (Qot) were lower than routine plasma etching. Furthermore, the decrease in capacitor size does not lead to an increase in leakage current density, indicating less plasma induced side-wall damage. We present a plasma-induced gate stack damage model which we demonstrate by using these two different etching configurations. These results show that NBE is effective in preventing plasma-induced damage at the high-k/Si interface and on the high-k oxide sidewall and thus improve the electrical performance of the gate structure.