No abstract

We present a multichip, mixed-signal VLSI system for spike-based vision processing. The system consists of an 80 x 60 pixel neuromorphic retina and a 4800 neuron silicon cortex with 4,194,304 synapses. Its functionality is illustrated with experimental data on multiple components of an attention-based hierarchical model of cortical object recognition, including feature coding, salience detection, and foveation. This model exploits arbitrary and reconfigurable connectivity between cells in the multichip architecture, achieved by asynchronously routing neural spike events within and between chips according to a memory-based look-up table. Synaptic parameters, including conductance and reversal potential, are also stored in memory and are used to dynamically configure synapse circuits within the silicon neurons.

Covert, low-power and low-bandwidth sensor networks for intelligent surveillance require imaging front-ends that make rudimentary decisions to perform or facilitate data compression. Typically, this front-end is composed of a standard Active Pixel Sensor (APS), an ADC and additional digital logic for image processing and communication control. As is expected, these systems are large (unless integrated) with considerable power budgets. To circumvent these problems, a CMOS imager that integrates circuits for basic decision-making and image compression on the focal plane is described. The chip is used as a low-power vision sensor and wake-up detector for these ad hoc networks.

Index Terms-CMOS image sensor, computation-on-readout (COR), delta-difference sampling (DDS), pixel-level analog-to-digital conversion (ADC), temporal difference imager.