The magnitude of the V T instability in conventional MOSFETs and MOS capacitors with SiO 2 /HfO 2 dual-layer gate dielectrics is shown to depend strongly on the details of the measurement sequence used. By applying time-resolved measurements (capacitance-time traces and charge-pumping measurements), it is demonstrated that this behavior is caused by the fast charging and discharging of preexisting defects near the SiO 2 /HfO 2 interface and in the bulk of the HfO 2 layer. Based on these results, a simple defect model is proposed that can explain the complex behavior of the V T instability in terms of structural defects as follows. 1) A defect band in the HfO 2 layer is located in energy above the Si conduction band edge. 2) The defect band shifts rapidly in energy with respect to the Fermi level in the Si substrate as the gate bias is varied. 3) The rapid energy shifts allows for efficient charging and discharging of the defects near the SiO 2 /HfO 2 interface by tunneling.

The electrical stability of CMOS devices with conventional gate dielectrics is commonly studied using static (DC) measurement techniques. By applying the same methods to MOS devices with alternative gate dielectrics, it has been shown that alternative gate stacks suffer from severe charge trapping and that the trapped charge is not stable, leading to fast transient charging components. In this paper timeresolved measurement techniques down to the p time range are applied to capture the fast transient component of the charge trapping observed in SiO, I Hf02 dual layer gate stacks. Furthermore, its impact on the device performance and reliability of n-channel FETs is discussed.

Strong polarity dependent charge trapping effects have been observed in as-deposited SiO2/Al2O3 gate stacks with TiN gate electrodes on n- and p-type Si substrates using current–voltage (I–V) and capacitance–voltage (C–V) sensing techniques. For substrate injection, electron trapping occurs mainly in the bulk of the Al2O3, resulting in positive voltage shifts for both I–V and C–V measurements. In the case of gate injection, positive charge trapping near the SiO2/Al2O3 interface leads to negative voltage shifts for C–V and positive shifts for I–V measurements. The polarity dependent charging effects are explained in terms of the difference in barrier height for substrate and gate injection and of the inherent asymmetry of the dual layer gate dielectric.

By means of catalytic chemical vapor deposition (CCVD) in-situ grown monolayer graphene field-effect transistors (MoLGFETs) and bilayer graphene transistors (BiLGFETs) are realized directly on oxidized silicon substrate without the need to transfer graphene layers. In-situ grown MoLGFETs exhibit the expected Dirac point together with the typical low on/off-current ratios. In contrast, BiLGFETs possess unipolar p-type device characteristics with an extremely high on/off-current ratio up to 1×10 7. The complete fabrication process is silicon CMOS compatible. This will allow a simple and low-cost integration of graphene devices for nanoelectronic applications in a hybrid silicon CMOS environment

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