Capacitance detection is a universal transduction mechanism used in a wide variety of sensors and applications. It requires an electronic front-end converting the capacitance variation into another more convenient physical variable, ultimately determining the performance of the whole sensor. In this paper we present a comprehensive review of the different signal conditioning front-end topologies targeted in particular at sub-femtofarad resolution. Main design equations and analysis of the limits due to noise are reported in order to provide the designer with guidelines for choosing the most suitable topology according to the main design specifications, namely energy consumption, area occupation, measuring time and resolution. A data-driven comparison of the different solutions in literature is also carried out revealing that resolution, measuring time, area occupation and energy/conversion lower than 100 aF, 1 ms 0.1 mm 2 , and 100 pJ/conv. can be obtained by capacitance to digital topologies, which therefore allow to get the best compromise among all design specifications.

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This paper introduces the electronic interface for a capacitive airborne particle matter detector. The proposed circuit relies on two matched ring oscillators and a mixer to detect the frequency difference induced by the deposition of a particle onto an interdigitated capacitor, which constitutes the load of one of the oscillators. The output of the mixer is digitized through a simple counter. In order to compensate the oscillation frequency offset of the two ring oscillators due to process and mismatch variations, a capacitive trimming circuit has been implemented. The sensor is connected to host through an I2C interface for communication and configuration. The sensor has been implemented using a standard 130-nm CMOS technology by STMicroelectronics and occupies 0.12-mm2 die area. Experimental measurements using talcum powder show a sensitivity of 60 kHz/fF and a 3σ resolution equal to 165 aF.

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Charge-Based Capacitance Measurement (CBCM) technique is a simple but effective technique for measuring capacitance values down to the attofarad level. However, when adopted for fully on-chip implementation, this technique suffers output offset caused by mismatches and process variations. This paper introduces a novel method that compensates the offset of a fully integrated differential CBCM electronic front-end. After a detailed theoretical analysis of the differential CBCM topology, we present and discuss a modified architecture that compensates mismatches and increases robustness against mismatches and process variations. The proposed circuit has been simulated using a standard 130-nm technology and shows a sensitivity of 1.3 mV/aF and a 20× reduction of the standard deviation of the differential output voltage as compared to the traditional solution.