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Summary This paper proposes a novel master slave (MS) flip‐flop design achieved by using only 18 transistors with a single‐phase clock and mixed topology. This design has lowest complexity, so flip‐flop basically focuses on the performance issue such as delay (TCQ) and average power consumption and compared with the other existing logic structured flip‐flops. The proposed circuit is implemented at 65‐nm Complementary Metal‐Oxide Semiconductor (CMOS), and 18‐nm finFET technology node using cadence virtuoso. The proposed flip‐flop architecture have outperformed transmission gate flip‐flop (TGFF) in terms of power (i.e., 74.52%). It is also showing improvement in terms of power as compared to 18‐transistor single‐phase clocking (18TSPC). This work also enhances the speed by reducing the delay minimum of 11.28% and PDP minimum of 37.18%. By using adaptive pass transistors topology to construct flip‐flop, the total area of the proposed flip‐flop reduces by a minimum of 4.78% with respect to 18TSPC, and also with the other flip‐flops reported in this paper. The proposed circuit can work properly within the frequency range up to 2‐GHz clock frequency. Monte Carlo simulations of Power and C to Q delay have been performed for 1000 samples.

Purpose A low power flip-flop circuit is designed for energy-efficient devices. Digital sequential circuits are in huge demand because every processor has most of the parts of digital circuit. The sequential circuits consist of a basic data storing element, a latch is used to store single bit data. The flip-flop takes a sufficient portion of the total chip area and overall power consumption as well. This study aims to the low power energy-efficient applications like laptops, mobile phones and palmtops. Design/methodology/approach This paper proposes a new type of flip-flop that consists of the only 16 transistors with a single-phase clock. The flip-flop has two blocks, master and slave latch. In this design, the authors have focused on only master latch, which includes a level restoring circuit. It is used to help the master latch in data retention process. The latch circuit has two inverters in back-to-back arrangement. The proposed flip-flop is implemented on 65 nm complementary metal oxide semiconductor technology using Cadence Virtuoso environment and compared with other reported flip-flops. Findings The proposed flip-flop architecture outperformed the peak percentage, i.e. 79.25% as compared to transmission gate flip-flop and a minimum of 20.02% compared to 18 T true single phase clocking (TSPC) improvement in terms of power. It also improved C to Q delay and power delay product. In addition, by reducing the number of transistors the total area of the proposed flip-flop is reduced by a minimum of 13.76% with respect to 18TSPC and existing flip-flop. For reliability checking the Monte Carlo simulation is performed for thousand samples and it is compared with the recently reported 18TSPC flip-flop. Originality/value This work is tested by using a test circuit with a load capacitor of 0.2 fF. The proposed work uses a new topology to work as master-slave. Power consumption of this technique is very less and it is best suitable for low power applications. This circuit is working properly up to 2 GHz frequency.

To read the data from the memory in each of the devices is crucial. In the modern-day VLSI, world need high-speed devices to satisfy the demand for application such as the Internet of Things (IoT) and System on Chip (Soc). We have implemented the different types of existing sense amplifiers to investigate the working and application point of view. Every sense amplifier has its own advantage. Each of the sense amplifiers is focusing basically on the charging and discharging of Bit Line (BL), Bit Line Bar (BLB) in case of Voltage sense and Data Line (DL), Data Line Bar (DLB) in case of current sense. The waveform of the Voltage sense and current sense clearly shown. Performance comparison based on Sensing Delay, Power, and Supply variation at UMC 65nm CMOS technology node using CADENCE Virtuoso tool.

The power efficiency and speed are two main concerns in any digital as well as analog circuit design. In this work, we analyze the pulse-triggered flip-flop (PTFF). In PTFF have two main stages, the pulse generator (PG) and the latch circuitry. We have utilized PG that has four transistors which is less than the number of transistors comparison to the previously used PGs. The design has been implemented on Cadence Virtuoso using 22nm CMOS cell library. The various parameters like data-to-output (D-to-Q) delay, leakage power and power-delay product (PDP) are being compared with existing flip-flop circuits like master-slave flip-flop (MSFF), DFF and conventional PTFF. The modified PTFF shows 24.3% improvement in D-to-Q delay and 18.1% improvement in PDP as contrast to the conventional PTFF.