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Fan-out Wafer Level Packaging (FOWLP) is one of the latest packaging trends in microelectronics. Mold embedding for this technology is currently done on wafer level up to 12"/300 mm diameter. For higher productivity and therewith lower costs larger mold embedding form factors are forecasted for the near future. Following the wafer level approach then the next step will be a reconfigured wafer size of 450 mm. An alternative option would be leaving the wafer shape and moving to panel sizes leading to Fan-out Panel Level Packaging (FOPLP). Sizes for the panel could range up to 24"×18" or even larger. For reconfigured mold embedding, compression mold processes are used in combination with liquid, granular or sheet compound. As a process alternative also lamination as used e.g. in PCB manufacturing can be taken into account.=Within this paper the evaluation of panel level compression molding with a target form factor of 24”*18” / 610×457 mm2 is described. The large panel size equals a typical PCB manufacturing full format and is selected to achieve process compatibility with cost efficient PCB processes. Here not only conventional compression molding is considered but also the new process compression mold lamination is introduced as a tool-less mold alternative. Panel level molding is compared to 8” and 12” wafer molding as well as to low cost PCB 24”×18” lamination focusing on manufacturing challenges, high volume capability and estimated cost. Technological focus of this study will be the evaluation of liquid, granular and sheet molding compound. This includes thorough material analysis regarding the process relevant material properties as reactivity or viscosity. One key process step for homogeneous large area embedding is material application before compression molding. Where sheet compounds already deliver a uniform material layer the application of liquid and granular compound must - e optimized and adapted for a homogeneous distribution without flow marks, knit lines and incomplete fills. Hence, dispense patterns of liquid and granular molding compounds are studied to achieve high yield and reliable mold embedding. In addition applicable thickness ranges, total thickness variations, void risks and warpage will be investigated for the different material types. The overall a process flow will be demonstrated for selected compression mold variants resulting in a 24”×18” / 610×457 mm2 FOPLP using PCB based redistribution layer (RDL) as low cost alternative to thin film technology. For=PCB based RDLs a resin coated copper sheet (RCC) is laminated on the reconfigured wafer or panel, respectively. Micro vias are drilled through the RCC layer to the die pads and electrically connected by Cu plating. Final process step is the etching of Cu lines using laser direct imaging (LDI) techniques for maskless patterning. All process steps are carried out on full format 24”×18” / 610×457 mm2

The constant drive towards further miniaturization and heterogeneous system integration leads to a need for new packaging technologies which also allow large area processing and 3D integration with potential for low cost applications. Large area mold embedding technologies and embedding of active components into printed circuit boards (Chip-in-Polymer) are two major packaging trends in this area. This paper describes the use of a novel S2iP (Stacked System in Package) interconnect technique using advanced molding process for multi chip embedding in combination with large area and low cost redistribution technology derived from printed circuit board manufacturing with a focus on integration of through mold vias for package stacking. The use of compression molding equipment with liquid or granular epoxy molding compounds for the targeted integration process flow is a new technology that has been especially developed to allow large area embedding of single chips but also of multiple chips or heterogeneous systems on wafer scale, typically 8” to 12”. Future developments will deal with panel sizes up to 470 × 370 mm2. The wiring of the embedded components in this novel type of SiP is done using PCB manufacturing technologies, i.e. a resin coated copper (RCC) film is laminated over the embedded components - whichever no matter which shape they are: a compression molded wafer or a larger rectangular area of a Molded Array Package (MAP). Interconnects are formed by laser drilling to die pads and electroplating - all of them making use of standard PCB processes. Thus, through vias which are standard features in PCB manufacturing and can be also integrated in the proposed process flow for mold embedding in combination with RCC based redistribution. Vias were drilled by laser or mechanically after RCC lamination and were metalized together with the vias for chip interconnection. Within this study different liquid and granular moldi- - ng compounds have been intensively evaluated on their processability. Via drilling process by laser and mechanical drilling is systematically developed and analyzed with focus on via diameter, pitch, mold thickness and molding compound composition and here especially on filler particle sizes and distribution. The feasibility of the entire process chain is demonstrated by fabrication of a Ball Grid Array (BGA) type of system package with two embedded dies and through mold vias allowing the stacking of these BGA packages. Finally, a technology demonstrator is described consisting of two BGAs stacked on each other and mounted on a base substrate enabling the electrical test of a daisy chain structure through the stacked module, allowing the evaluation of the technology and the applied processes

As the development of microelectronics is still driving towards further miniaturization, Flip Chip technology has been widely accepted as a means for maximum miniaturization with additional advantages. These are shortest interconnect length for minimum signal disturbance and simultaneous interconnection leading to reduced process times especially for high I/O counts and for RF applications. Flip Chip technology allows for reliabilities required for automotive applications, but to achieve this goal, a plastic encapsulant, the so called underfiller, has to be used. Conventionally a liquid epoxy resin is dispensed near the Flip Chip and is driven by capillary action under the chip. New material developments for transfer molding allow now underfilling and overmolding in one single transfer molding step. Existing standard equipment for encapsulation can be used and no additional process step for underfill dispensing is required. Molded Flip Chips have the potential of high reliability as the low CTE of the flip chip molding compound reduces the thermal mismatch. State of the art in FC molding is the encapsulation of Single Chip Packages as BGA or CSP. Trends of the market driving at SIPS with an integration of different devices as e.g. SMD and FC. Therefore the high reliable encapsulation of these hybrid packages with inhomogeneous topography is the future goal.Fraunhofer IZM. This test vehicle for process evaluation allows the encapsulation and underfilling of a single flip chip.Process development is described with a focus on Flip Chip and SIP molding challenges. Here the encapsulation process demands are filling of extremeIy small gaps without air entrapments, undisturbed bond integrity while molding at temperatures near melting point of the solder and increased pressures and venting of the mold. Device reliability demands are reduced warpage and optimum adhesion of the molding compound to solder mask, solder and die, even in harsh environment.