Process variation creates core-speed discrepancy among the core in many-core platforms. Random variation is one of the important components that contribute into core-speed discrepancy. In the paper, a novel technique is proposed that uses footer transistors to reduce the delay and power in a manycore platform. Process variation is due to many fundamental deficiencies, impurities, and imperfections during the fabrication process at the nano-scale technologies. The results of this variation have a direct impact on two key parameters of the CMOS transistor: threshold voltage and gate length, which have major implication on the core speed and power. The random component of this variation is mostly attributed to the randomdopant fluctuation, which results in threshold voltage discrepancy among the cores. The proposed technique reduces the random dopant fluctuation by lowering the dopant density and then compensating the threshold voltage using a footer transistor minimizing the static power dissipation.