By modification of the electrode-solid-electrolyte interface with graphene, transit from valence change memories (VCM) to electrochemical metallization memories (ECM) in the cell Ta(C)/Ta2 O5 /Pt is demonstrated, thus, bridging both mechanisms. The ECM operation is discussed in the light of Ta-cation mobility in TaOx . The crucial role of electrochemical processes and moisture in the resistive switching process is also highlighted.

Metal–insulator–semiconductor structures with a layer of silicon nanocrystals embedded within the SiO2 layer at a tunneling distance from a p-type silicon substrate and fabricated using chemical vapor deposition, oxidation, and annealing, exhibited charge trapping, determined from the capacitance–voltage (C–V) characteristics, which abruptly increased at fields above 2.5 MV/cm. Electrons or holes are trapped when biasing the structure into inversion or accumulation, respectively, and retention of trapped charge is demonstrated. The I–V characteristics exhibit an N-shaped form, indicating screening effects due to charging; an initial current spike, attributed to transient charging of nanocrystals, occurs at the same voltage causing abrupt C–V shift increase, with Fowler–Nordheim current rising at higher voltages. These structures are promising for memory device applications.

Thin films of the high-k dielectric Y2O3 are grown on Si (001) substrates by e-beam evaporation in ultrahigh vacuum (UHV), aiming at correlating structural quality with electrical behavior. Films grown at high temperature of ∼450 °C have reproducibly good epitaxial crystalline quality although they exhibit poor electrical behavior. The best electrical properties are measured in films grown at a low to intermediate temperature range around 200 °C, although these films have inferior structural quality, exhibiting texturing or polycrystallinity. A possible explanation for the observed low leakage current (∼10−6 A/cm2 at +1 V) in these films is the presence of a thick (15–20 Å) and uniform interfacial amorphous layer typically formed during growth because of the oxidation of the silicon substrate. This layer is significantly reduced in samples grown at high temperature, while it almost disappears after in situ annealing to 650 °C in UHV, producing sharp interfaces and very good, stoichiometric crystalline Y2O3 epitaxial layers.

We analyze a method to selectively grow straight, vertical gallium nitride nanowires by plasma-assisted molecular beam epitaxy (MBE) at sites specified by a silicon oxide mask, which is thermally grown on silicon (111) substrates and patterned by electron-beam lithography and reactive-ion etching. The investigated method requires only one single molecular beam epitaxy MBE growth process, i.e., the SiO2 mask is formed on silicon instead of on a previously grown GaN or AlN buffer layer. We present a systematic and analytical study involving various mask patterns, characterization by scanning electron microscopy, transmission electron microscopy, and photoluminescence spectroscopy, as well as numerical simulations, to evaluate how the dimensions (window diameter and spacing) of the mask affect the distribution of the nanowires, their morphology, and alignment, as well as their photonic properties. Capabilities and limitations for this method of selective-area growth of nanowires have been identified. A window diameter less than 50 nm and a window spacing larger than 500 nm can provide single nanowire nucleation in nearly all mask windows. The results are consistent with a Ga diffusion length on the silicon dioxide surface in the order of approximately 1 μm.

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