The design of digital VLSI circuits must take energy efficiency into consideration. Reducing the circuit’s power consumption, which has been a major issue since 2000, would increase the necessity for energy efficiency. Error-tolerant systems heavily rely on approximate computation methods to increase power efficiency. The key factors of the system’s overall power consumption and area computation are adders and multipliers, which are also crucial in approximate computing. High energy-efficiency adders can be used to create additional multipliers. In order to dramatically minimize power consumption, this work builds and implements 8×8 Dadda multipliers using 1 bit approximation adders. Calculation is sped up by using the Dadda multiplier. In turn, by reducing propagation latency, the suggested design lowers power consumption in digital CMOS circuitry. The proposed multiplier design with approximate adders, which was created in Verilog HDL, simulated in FPGA, and synthesized in FPGA platform, is implemented on an ASIC platform using Cadence 90 nm Technology. The Gaussian filter additionally employs the proposed Dadda multiplier for picture denoising in approximation adder-based image processing applications.