Filtering of the measurement signals using digital brick-wall comb filters in frequency domain developed by the authors and measurement of the settling times of DACs are discussed in this paper. Results of the investigations made have shown that digital brick-wall comb filters are capable of reducing noise level by 10 times while keeping measurement signal undistorted. Investigation of the developed settling time measurement algorithm has determined influence of the internal noise of the sampling converter, noise of the transmission line, ADC and other sources of noise to the settling time measurement errors. It has been proved that by using the earlier developed measurement converter and the proposed digital filtering of the DAC signal it is possible to measure settling times of 12-14 bit DACs.

New specialized sampling converter for signal timescale transformation and algorithm of digital signal processing for automated measurement of settling times of fast digital-to-analogue converters is represented. The new sampling device with numerically controlled oscillators allows us realization of different types of the timescale transformation. Usage of Σ∆ analogue-to-digital converter and first-in first-out memory allows us significant simplification of the device. The equations of timescale transformation ratio and sampling step are presented. A method using a brick-wall comb filter in frequency domain to filter measurement signal has been developed. It is shown that such filtering allows us significant reduction of noise of measurement signal. A new method and algorithm using a brick-wall comb filter and averaging of filtered signal has been developed. Results of the research of developed digital signal processing algorithm are submitted.

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Developed sampling device and algorithm of digital signal processing for automated measurement of settling times of fast DACs is represented. The new sampling device with numerically controlled oscillators allows realizing of the different types of the time scale transformation. Using of sigma-delta ADC and FIFO memory allows significant simplification of the device. The equations of time scale transformation ratio and sampling step are presented. Results of the research of developed digital signal processing algorithm are submitted.

No abstract