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In this paper, we present the performance of multi-user transmitter pre-processing (MUTP) assisted coded-interleave division multiple access (IDMA) system over correlated frequency-selective channels for downlink communication. We realize MUTP using singular value decomposition (SVD) technique, which exploits the channel state information (CSI) of all the active users that is acquired via feedback channels. We consider the MUTP technique to alleviate the effects of co-channel interference (CCI) and multiple access interference (MAI). To be specific, we estimate the CSI using least square error (LSE) algorithm at each of the mobile stations (MSs) and perform vector quantization using Lloyd's algorithm, and feedback the bits that represents the quantized magnitudes and phases to the base station (BS) through the dedicated low rate noisy channel. Finally we recover the quantized bits at the BS to formulate the pre-processing matrix. The performance of MUTP aided IDMA systems are evaluated for five types of delay spread distributions pertaining to long-term evolution (LTE) and Stanford University Interim (SUI) channel models. We also compare the performance of MUTP with minimum mean square error (MMSE) detector for the coded IDMA system. The considered TP scheme alleviates the effects of CCI with less complex signal detection at the MSs when compared to MMSE detector. Further, our simulation results reveal that SVD-based MUTP assisted coded IDMA system outperforms the MMSE detector in terms of achievable bit error rate (BER) with low signal-to-noise ratio (SNR) requirement by mitigating the effects of CCI and MAI.

We describe an efficient, fully-parallel Network of Programmable Logic Array (NPLA)-based realization of iterative decoders for structured LDPC codes. The LDPC codes are developed in tandem with the underlying VLSI implementation technique, without compromising chip design constraints. Two classes of codes are considered: one, based on combinatorial objects derived from difference sets and generalizations of non-averaging sequences, and another, based on progressive edge-growth techniques. The proposed implementation reduces routing congestion, a major issue not addressed in prior work. The operating power, delay and chip-size of the circuits are estimated, indicating that the proposed method significantly outperforms presently used standard-cell based architectures. The described LDPC designs can be modified to accommodate widely different requirements, such as those arising in recording systems, as well as wireless and optical data transmission devices.

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