This paper reports an optimized and highly sensitive piezoresistive SU-8 nanocomposite microcantilever sensor and its application for detection of explosives in vapour phase. The optimization has been in improving its electrical, mechanical and transduction characteristics. We have achieved a better dispersion of carbon black (CB) in the SU-8/CB nanocomposite piezoresistor and arrived at an optimal range of 8-9 vol% CB concentration by performing a systematic mechanical and electrical characterization of polymer nanocomposites. Mechanical characterization of SU-8/CB nanocomposite thin films was performed using the nanoindentation technique with an appropriate substrate effect analysis. Piezoresistive microcantilevers having an optimum carbon black concentration were fabricated using a design aimed at surface stress measurements with reduced fabrication process complexity. The optimal range of 8-9 vol% CB concentration has resulted in an improved sensitivity, low device variability and low noise level. The resonant frequency and spring constant of the microcantilever were found to be 22 kHz and 0.4 N m(-1) respectively. The devices exhibited a surface stress sensitivity of 7.6 ppm (mN m(-1))(-1) and the noise characterization results support their suitability for biochemical sensing applications. This paper also reports the ability of the sensor in detecting TNT vapour concentration down to less than six parts per billion with a sensitivity of 1 mV/ppb.

Abstract-In this paper, we investigate the quality of MOSFET gate stacks where high-k materials are implemented as gate dielectrics. We evaluate both drain-and gate-current noises in order to obtain information about the defect content of the gate stack. We analyze how the overall quality of the gate stack depends on the kind of high-k material, on the interfacial layer thickness, on the kind of gate electrode material, on the strain engineering, and on the substrate type. This comprehensive study allows us to understand which issues need to be addressed in order to achieve improved quality of the gate stack from a 1/f noise point of view.Index Terms-Drain noise, gate noise, high-k dielectric, MOSFET, 1/f noise.

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Abstract-The difficulty to fabricate and control precisely defined doping profiles in the source/drain underlap regions of FinFETs necessitates the use of undoped gate underlap regions as the technology scales down. We present a phenomenon called the gate fringe-induced barrier lowering (GFIBL) in FinFETs with undoped underlap regions. In these FinFETs, we show that the GFIBL can be effectively used to improve I on . We propose the use of high-κ spacers in such FinFETs to enhance the effect of GFIBL and thereby achieve better device and circuit performance. When compared with the underlap FinFETs with Si 3 N 4 spacers, with κ = 20 spacers, we show that it is possible to achieve an 80% increase in I on at iso-I off conditions and a 15% decrease in the inverter delay for a fan-out of four.Index Terms-CMOS scaling, FinFET, fringe-induced barrier lowering (GFIBL), high-κ materials, short-channel effects (SCEs).

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