Extremely large capacity is needed in the next decade for the application of optical storage memory. To achieve higher data transfer rates page-oriented optical memories have been suggested as replacements for current bit-serial memories in large-capacity memory systems. Although many research endeavors have been concentrated on the development of page-oriented memory, a practical optical storage system also depends on the demonstration of optical read head technologies that are capable of reading and processing data in page-oriented fashion. This thesis explores the possibility for implementing a device to interface an ultra-high density optical storage media with an existing electronic computing hardware. The page-oriented data read capability of a next generation read-head device is demonstrated using current CMOS technology, which is compatible with other electronic circuitry. The circuit was designed and fabricated using a conventional CMOS process. A CMOS based photodetector, which is an unconventional photonic device, was integrated monolithically onto each individual pixel on the chip, as well as the CMOS photoreceiver circuit and other control units. A 2-D pixel array was presented to realize the page-read mode. Test results verify our design of the high sensitivity photoreceiver circuit and high system throughput of the pixel array structure. The final system implementation is expected to serve as the front-end in a page-oriented optical memory system. iv In the first part of the thesis, a brief introduction to the motivation and background of this project is given. A literature review is presented with an emphasis placed on the design of high performance photoreceivers. The second part of the thesis describes the design, simulation and analysis of the proposed read-head device. Individual components and the whole system are characterized and simulation results shown. While the final system is designed for implementation in a 0.35µm CMOS technology, fabrication costs limited the project to implementation of a test chip in 1.5µm CMOS technology. Finally, the performance evaluation of the fabricated test chip is presented. v vi ACKNOWLEDGEMENTS First and at the very outset, I'd like to express my deep gratitude to Dr. Beyette for his mentoring and guidance on this project, as well as on other academic and life issues critical to my future study. Great thanks for Dr. Boyd, Dr. Ferendeci and Dr. Harold Carter of reviewing my thesis and serving as my thesis committee member. Deep appreciations toward Arvind Chokhani and Sathya Vageeshwar for their inva luable discussions on receiver design and Jianjing for his help on the system test. I would also like to thank my colleagues and seniors in our PSDL group, Prashant Bhadri, Prosenjit Mal, Kuntao Ye,

The ever increasing demand for communication bandwidth and system interconnectivity has been a motivating factor behind the integration of optoelectronics device and conventional data processing circuitry. Over the last two decades, fiber optic components have become the dominant technology in the telecommunications industry. In last 5 years, optical interconnection techniques have been suggested as a solution to the interconnect density and bandwidth problems faced by electrical systems at the cabinet, PC-board and even chip level. Based on the smart pixel architectures in the last decade, the proposed chip monolithically integrates optical sensors with silicon CMOS based circuitry. This project incorporates an instruction fetch unit (IFU), that fetches the instructions from an external host computer, and a 2D-array of one-bit smart pixels called the processing element (PE). Each PE consists of an ALU, control logic, dual port register memory bank, photo-receiver circuit and associated driver circuits. By tiling these smart pixels in 2D, it is possible to form a programmable smart pixel array that is well suited to read optical page-oriented data types. The CASPR chip contains a 4x4 array of PEs connected to a single IFU. Inter PE communication has been established through nearest neighbor communication. Simultaneous communication to all the PEs is possible through global communication. The instruction set for this architecture is 17-bit long. The chip has been successfully fabricated in 0.5µ technology. We present in this paper the design and initial test results from the recent fabrication.

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