In this paper, we present triggered instructions, a novel control paradigm for arrays of processing elements (PEs) aimed at exploiting spatial parallelism. Triggered instructions completely eliminate the program counter and allow programs to transition concisely between states without explicit branch instructions. They also allow efficient reactivity to inter-PE communication traffic. The approach provides a unified mechanism to avoid over-serialized execution, essentially achieving the effect of techniques such as dynamic instruction reordering and multithreading, which each require distinct hardware mechanisms in a traditional sequential architecture.Our analysis shows that a triggered-instruction based spatial accelerator can achieve 8× greater area-normalized performance than a traditional general-purpose processor. Further analysis shows that triggered control reduces the number of static and dynamic instructions in the critical paths by 62% and 64% respectively over a program-counter style spatial baseline, resulting in a speedup of 2.0×.

There has been recent interest in exploring the acceleration of nonvectorizable workloads with spatially programmed architectures that are designed to efficiently exploit pipeline parallelism. Such an architecture faces two main problems: how to efficiently control each processing element (PE) in the system, and how to facilitate inter-PE communication without the overheads of traditional shared-memory coherent memory. In this article, we explore solving these problems using triggered instructions and latency-insensitive channels. Triggered instructions completely eliminate the program counter (PC) and allow programs to transition concisely between states without explicit branch instructions. Latency-insensitive channels allow efficient communication of inter-PE control information while simultaneously enabling flexible code placement and improving tolerance for variable events such as cache accesses. Together, these approaches provide a unified mechanism to avoid overserialized execution, essentially achieving the effect of techniques such as dynamic instruction reordering and multithreading. Our analysis shows that a spatial accelerator using triggered instructions and latency-insensitive channels can achieve 8 × greater area-normalized performance than a traditional general-purpose processor. Further analysis shows that triggered control reduces the number of static and dynamic instructions in the critical paths by 62% and 64%, respectively, over a PC-style baseline, increasing the performance of the spatial programming approach by 2.0 ×.

Âñåðîññèéñêèé íàó÷íî-èññëåäîâàòåëüñêèé èíñòèòóò ïðîòèâîïîaeàðíîé îáîðîíû Ì×Ñ Ðîññèè (Ðîññèÿ, 143903, ã. Áàëàøèõà Ìîñêîâñêîé îáë., ìêð. ÂÍÈÈÏÎ, 12) ÐÅÇÞÌÅ Ââåäåíèå. AEåëåçîáåòîííûå êîíñòðóêöèè èç òÿaeåëîãî áåòîíà ïîâûøåííîé âëàaeíîñòè (áîëåå 3,5 %) èìåþò ñêëîííîñòü ê âçðûâîîáðàçíîìó ðàçðóøåíèþ, êîòîðîå ìîaeåò ïðèâåñòè ê ïðåaeäåâðåìåííîìó íàñòóïëåíèþ ïðåäåëà îãíåñòîéêîñòè òàêèõ êîíñòðóêöèé è ÷àñòè÷íîìó èëè ïîëíîìó îáðóøåíèþ çäàíèé è ñîîðóaeåíèé. Ïîâûøåííàÿ âëàaeíîñòü aeåëåçîáåòîííûõ êîíñòðóêöèé îáû÷íî âñòðå÷àåòñÿ â ïîäçåìíûõ ñîîðóaeåíèÿõ è âî âíîâü âîçâîäèìûõ çäàíèÿõ. Îãíåñòîéêîñòü aeåëåçîáåòîííûõ òþáèíãîâ ïîäçåìíûõ ñîîðóaeåíèé â çíà÷èòåëüíîé ñòåïåíè çàâèñèò îò âçðûâîîáðàçíîãî (õðóïêîãî) ðàçðóøåíèÿ áåòîíà ïðè âîçäåéñòâèè âûñîêèõ òåìïåðàòóð ïîaeàðà íà ïîâåðõíîñòü îáäåëêè òîííåëÿ. Ìàòåðèàëû è ìåòîäû.  êà÷åñòâå îáúåêòà èññëåäîâàíèÿ áûëè âûáðàíû aeåëåçîáåòîííûå òþáèíãè èç òÿaeåëîãî áåòîíà âëàaeíîñòüþ 6 % ñ äîáàâêîé ïîëèïðîïèëåíîâîé ôèáðû â êîëè÷åñòâå 1 êã/ì 3 . Ïðîâåäåíû êðóïíîìàñøòàáíûå îãíåâûå èñïûòàíèÿ íà ñïåöèàëüíî èçãîòîâëåííîì ñòåíäå ïðè íàãðóaeåíèè îáðàçöîâ âåðòèêàëüíîé è ãîðèçîíòàëüíîé íàãðóçêîé. Ðåçóëüòàòû è îáñóaeäåíèå. Ïðåäñòàâëåíû îñíîâíûå ðåçóëüòàòû ýêñïåðèìåíòàëüíîãî èññëåäîâàíèÿ îãíåñòîéêîñòè aeåëåçîáåòîííûõ òþáèíãîâ ñ äîáàâêîé ïîëèïðîïèëåíîâîé ôèáðû è áåç íåå. Ïî ðåçóëüòàòàì óñòàíîâëåíî, ÷òî ïðåäåë îãíåñòîéêîñòè aeåëåçîáåòîííîãî òþáèíãà ñ äîáàâêîé ïîëèïðîïèëåíîâîé ôèáðû ñîãëàñíî ÃÎÑÒ 30247.0-94 ñîñòàâèë íå ìåíåå 125 ìèí (REI 120). Ðàçðàáîòàíà àíàëèòè÷åñêàÿ ìîäåëü îöåíêè îãíåñòîéêîñòè. Äëÿ ðåøåíèÿ òåïëîòåõíè÷åñêîé çàäà÷è ïðîâåäåí ÷èñëåííûé ýêñïåðèìåíò ñ ïîìîùüþ ïðîãðàììíîãî êîìïëåêñà "ANSYS". Ïðåäëîaeåíà àíàëèòè÷åñêàÿ çàâèñèìîñòü îïðåäåëåíèÿ äîïîëíèòåëüíîãî òåìïåðàòóðíîãî ïðîãèáà äëÿ ãåîìåòðè÷åñêè íåëèíåéíîãî ýëåìåíòà. Ðàñ÷åò ïðåäåëà îãíåñòîéêîñòè aeåëåçîáåòîííîãî òþáèíãà ñ äîáàâêîé ïîëèïðîïèëåíîâîé ôèáðû ïî ðàçðàáîòàííîé àíàëèòè÷åñêîé ìîäåëè ñ ó÷åòîì ðàíåå ïîëó÷åííûõ ïðî÷íîñòíûõ è òåïëîòåõíè÷åñêèõ õàðàêòåðèñòèê ïîäòâåðäèë ðåçóëüòàòû îãíåâûõ èñïûòàíèé: ïðåäåë îãíåñòîéêîñòè ñîñòàâèë REI 120. Çàêëþ÷åíèå. Èñïîëüçîâàíèå äëÿ îãðàaeäàþùèõ êîíñòðóêöèé òîííåëÿ aeåëåçîáåòîííûõ òþáèíãîâ èç ôèáðîáåòîíà ñ ïîëèïðîïèëåíîâîé ôèáðîé ïîçâîëèò çíà÷èòåëüíî ñíèçèòü çàòðàòû íà óñòðîéñòâî îãíåçàùèòû è ñîêðàòèòü ñðîêè ñòðîèòåëüñòâà.Êëþ÷åâûå ñëîâà: ñòàíäàðòíûé òåìïåðàòóðíûé ðåaeèì ïîaeàðà; òåïëîòåõíè÷åñêàÿ çàäà÷à; ñòàòè÷åñêàÿ (ïðî÷íîñòíàÿ) çàäà÷à; âçðûâîîáðàçíîå (õðóïêîå) ðàçðóøåíèå áåòîíà; îáäåëêà òîííåëÿ.

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