We present a framework for the synthesis of phase polynomials that addresses both cases of full connectivity and partial connectivity for NISQ architectures. In most cases, our algorithms generate circuits with lower CNOT count and CNOT depth than the state of the art or have a significantly smaller running time for similar performances. We also provide methods that can be applied to our algorithms in order to trade an increase in the CNOT count for a decrease in execution time, thereby filling the gap between our algorithms and faster ones.

We present a framework for the synthesis of phase polynomials that addresses both cases of full connectivity and partial connectivity for NISQ architectures. In most cases, our algorithms generate circuits with lower CNOT count and CNOT depth than the state of the art or have a significantly smaller running time for similar performances. We also provide methods that can be applied to our algorithms in order to trade an increase in the CNOT count for a decrease in execution time, thereby filling the gap between our algorithms and faster ones.

The Clifford+T gate set is commonly used to perform universal quantum computation. In such setup the T gate is typically much more expensive to implement in a fault-tolerant way than Clifford gates. To improve the feasibility of fault-tolerant quantum computing it is then crucial to minimize the number of T gates. Many algorithms, yielding effective results, have been designed to address this problem. It has been demonstrated that performing a pre-processing step consisting of reducing the number of Hadamard gates in the circuit can help to exploit the full potential of these algorithms and thereby lead to a substantial T -count reduction. Moreover, minimizing the number of Hadamard gates also restrains the number of additional qubits and operations resulting from the gadgetization of Hadamard gates, a procedure used by some compilers to further reduce the number of T gates. In this work we tackle the Hadamard gate reduction problem, and propose an algorithm for synthesizing a sequence of Pauli rotations with a minimal number of Hadamard gates. Based on this result, we present an algorithm which optimally minimizes the number of Hadamard gates lying between the first and the last T gate of the circuit.