In this study we have investigated the reactive ion etching of 60 μm diam, 200 μm deep holes in 3 in. diam semi-insulating GaAs wafer using a combination of CCl2F2 and CCl4 gases for fabrication of through substrate via holes for grounding in monolithic microwave integrated circuits (MMICs). The effect of process parameters viz. pressure, CCl4/CCl2F2 ratio, and power on GaAs etch rate and resultant etch profile was investigated. Two kind of masks, photoresist and Ni, were used to etch GaAs and their performance was compared by investigating effect on etch rate, etch depth, etch profile, and surface morphology. The etch profile, etch depth, and surface morphology of as-etched samples were characterized by scanning electron microscopy. The desired 200 μm deep strawberry profile, with a top normaldiam=60±10 μm and bottom normaldiam=180±10 μm, was obtained at 40 mTorr process pressure with an average etch rate ∼1.3 μm/min using Ni mask. The vias were then metallized by depositing a thin seed layer of Ti/Au (1000 Å) using radio frequency sputtering and Au (5 μm) electroplated to connect the front side pad and back side ground plane. The parasitic inductance offered by these vias was ∼76 pH. The developed process was then integrated into the MMIC process line and a 16-18 GHz amplifier was fabricated using grounding vias with yield >90%. © 2003 The Electrochemical Society. All rights reserved.

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Developments in the etching process for fabrication of back-side via holes in GaAs based monolithic microwave integrated circuits are reviewed. Attention is focused on critical issues concerning via hole fabrication. The requirements of the process of via hole etching are considered. The suitability of various fabrication techniques, and the associated chemistry, has been examined. The effects of various process parameters such as power, pressure, and gas flow rate on the etch characteristics have been discussed. The influence of the masking material, via hole dimensions and the wafer size on the etch characteristics have been discussed from the point of view of increasing packing density in advanced chip fabrication. Finally, the state of the art and the issues concerning the via hole etching process are described.

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