The application domains of portable embedded real-time systems range from safety-critical applications like electronic control units in the automotive sector to entertainment applications like digital cameras and setup boxes in the consumer electronics sector. These systems attract users with multiple and sophisticated functionalities in a single system. The developments in VLSI technology have enabled IC manufacturers to incorporate more features in a single die, which facilitates these multipurpose systems. The increase in features and functionalities has a direct impact on power consumption and has to be strictly accounted for in the design of these embedded systems. The possibility of achieving low power consumption is obtained by using only effective software techniques along with the hardware powersaving methods. The dynamic power management techniques with the support of real-time operating systems (RTOSs) provided in recent microcontrollers enable better power management using software control. The scheduling of tasks in real-time systems is based on the worst-case execution time (WCET), whereas tasks based on their environmental conditions may complete their execution before the WCET. This leads to increased laxity (slack time) and reduced utilization of the CPU. This paper proposes Fixed Window DynaClam, a dynamic reclamation algorithm, to effectively utilize slack time. The clock frequency of the processor is slowed down by reclaiming the available slack time to reduce the energy consumption. The Fixed Window DynaClam algorithm is implemented for nonpreemptive periodic tasks in the controllers with dynamic voltage and frequency scaling power management features. The novelty of the algorithm is that the clock frequency is not only adjusted based on the real-time demands of the tasks but also does not overload the kernel of the RTOS as the complexity is on the lower side.

Abstract:Embedded systems have geared up their applications in the field of smart phones, mobile devices, automobiles, and medical instrumentation. Along with the growth of technology, the functional requirements of the systems have also grown multifold. To accommodate these ever increasing functional requirements, the hardware should be designed to include the maximum capability, which in turn increases power consumption. Thus this has to be dynamically managed using software techniques. The dynamic voltage and frequency scaling (DVFS) feature provided in most of the recent processors has enabled power optimization through software. With this feature the processor operating frequency can be reduced on the fly through software. This paper proposes two approaches. In the first one, the hyper period-based method (HPBM), the slow down factor is calculated for the hyper period and the second method involves applying uniform slow down with frequency inheritance (USFI) with a hyper plane exact test (HET). Both approaches aim to calculate slow down factors for the tasks to be executed in the processors with the DVFS feature. The main objective of this work is to provide energy optimized scheduling as well as to minimize the overheads in slow down factor calculations.