Abstract-This paper shows that existing delay-based testing techniques for power gating exhibit fault coverage loss due to unconsidered delays introduced by the structure of the virtual voltage power-distribution-network (VPDN). To restore this loss, which could reach up to 70.3% on stuck-open faults, we propose a design-for-testability (DFT) logic that considers the impact of VPDN on fault coverage in order to constitute the proper interface between the VPDN and the DFT. The proposed logic can be easily implemented on-top of existing DFT solutions and its overhead is optimized by an algorithm that offers trade-off flexibility between test-application-time and hardware overhead. Through physical layout SPICE simulations, we show complete fault coverage recovery on stuck-open faults and 43.2% testapplication-time improvement compared to a previously proposed DFT technique. To the best of our knowledge, this paper presents the first analysis of the VPDN impact on test quality.

obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.The WestminsterResearch online digital archive at the University of Westminster aims to make the research output of the University available to a wider audience. Copyright and Moral Rights remain with the authors and/or copyright owners.Whilst further distribution of specific materials from within this archive is forbidden, you may freely distribute the URL of WestminsterResearch: ((http://westminsterresearch.wmin.ac.uk/). Abstract-In this paper, we show that BTI aging of MOS transistors, together with its detrimental effect for circuit performance and lifetime, presents considerable benefits for static power consumption due to sub-threshold leakage current reduction. Indeed, static power reduces considerably, making CMOS circuits more energy efficient over time. Static power reduction depends on transistor stress ratio and operating temperature. We propose a simulation flow allowing us to properly evaluate the BTI aging of complex circuits in order to estimate BTI-induced power reduction accurately. Through HSPICE simulations, we show 50% static power reduction after only 1 month of operation, which exceeds 78% in 10 years. BTI aging benefits for power consumption are also proven with experimental measurements.

In this paper, we propose a novel technique to detect recycled ICs via an on-chip, coarse-grained aging sensor, which can be applied to low-power circuits featuring power gating. The sensor detects the increase in the power-rail discharge time of power-gated circuits, when the circuit enters the sleep condition. Through HSPICE simulations, we prove that power network discharge time (τ dV ) is extremely sensitive to the age of the circuit. Indeed, after only 1 month of operation, τ dV increases by more than 3X and, after 1 year, its increase exceeds 7X. Our technique enables the detection of recycled ICs with a very high confidence and is a considerably more sensitive indicator of an aged device that alternative solutions relying on fine-grained performance degradation sensors.

In this paper, we present a novel coarse-grained technique for monitoring online the bias temperature instability (BTI) aging of circuits by exploiting their power gating infrastructure. The proposed technique relies on monitoring the discharge time of the virtual-power-network during standby operations, the value of which depends on the threshold voltage of the CMOS devices in a power-gated design (PGD). It does not require any distributed sensors, because the virtual-powernetwork is already distributed in a PGD. It consists of a hardware block for measuring the discharge time concurrently with normal standby operations and a processing block for estimating the BTI aging status of the PGD according to collected measurements. Through SPICE simulation, we demonstrate that the BTI aging estimation error of the proposed technique is less than 1% and 6.2% for PGDs with static operating frequency and dynamic voltage and frequency scaling, respectively. Its area cost is also found negligible. The power gating minimum idle time (MIT) cost induced by the energy consumed for monitoring the discharge time is evaluated on two scalar machine models using either x86 or ARM instruction sets. It is found less than 1.3× and 1.45× the original power gating MIT, respectively. We validate the proposed technique through accelerated aging experiments conducted with five actual chips that contain an ARM cortex M0 processor, manufactured with a 65 nm CMOS technology.

hand, the method proposed in [11] requires storing 6656 bits that were decomposed into 3 tables (128 2 18, 128 2 18 and 128 2 16) providing an accuracy of 16.7 bits.As can be seen, the proposed architecture reduces the LUT size by 5.7% generating the logarithm approximation with the same precision. Both methods have been pipelined to have as high a throughput as possible. Our approach exhibits similar working frequency to [11] with lower latency. The critical path in our approach is the delay of Block RAM in the Virtex-II PRO. VI. CONCLUSIONA low cost, high speed logarithm approximation has been proposed based on Mitchell's method with a correction stage composed of piecewise linear interpolation and a LUT correction. The Mitchell error interval is divided into four regions that are approximated with straightlines with power-of-two slopes and a truncated mantissa. The accuracy is increased by adding a small LUT or a multipartite table that stores the residual error obtained after the piecewise correction stage. The proposed approach achieves higher accuracy than similar low-cost piecewise linear interpolation methods found in the literature and lower area than LUT-based methods. REFERENCES[1] T. A. Brubaker and J. C. Becker, "Multiplication using logarithms implemented with read-only memory," IEEE Trans.