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This paper presents an improvement on the RF-DC rectifier with the self-bias diode-connected MOS transistors to achieve a wide input power range. The proposed design utilized a dual voltage polarity to bias the rectifying PMOS and NMOS with a positive and negative DC potential respectively. This biasing potential enables the gate of the transistor to be boosted above the output voltage or below the rectifier ground to minimize the leakage current. A proposed 3-stage rectifier design is simulated using a 55nm BCD technology and occupies an area of 0.064 mm 2 . The post-layout simulation results show a 75.3% power conversion efficiency (PCE) at -7dBm, -22.5dBm sensitivity and an input power range of 21.2dB when operating at the 900MHz input RF frequency with a 100kΩ load.

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