The intervention of noise into images during data acquisition and transmission is inevitable. Hence, the denoising of such affected images is essential in order to have effective image analysis where it needs image filtering. The Gabor filter is widely adapted in various image processing applications for feature extraction, texture analysis, pattern analysis, etc. The Gabor-based filtering technique adopted in work is aimed for image filtering in order to extract edges. The design of a low-power portable system deploys hardware accelerators to achieve high performance per watt in feature extraction and edge detection. In this paper, an image denoising hardware accelerator model is mapped from the Gabor filter function. Moreover, hardware models for realizing various parameters involved in the Gabor function are also presented. A MATLAB model for the proposed denoising hardware accelerator is simulated and performance is measured in terms of the peak-signal-to-noise ratio, mean square error, histograms and compared with algorithm level performance reported in the literature. It is observed that the proposed hardware architecture model showed better performance compared to the mathematical models reported in the literature. However, the key limitation is the degradation of hardware performance due to a truncation or rounding of the sample’s word length.

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Compared to Binary Content Addressable Memory (BiCAM) there are many applications for Ternary Content Addressable Memory (TCAM) as a search engine. But TCAM consumes more power than BiCAM. So, the saving of TCAM power consumption is the main objective of numerous designs. Precharge phase of the TCAM leads to more power consumption. Newly, a precharge free NOR type BiCAM has been suggested but it takes more time for its operation. Here, precharge free high speed NOR type TCAM is proposed. The proposed TCAM architecture takes power same as precharge free NOR type TCAM but its delay has been reduced by 84% . Simulations performed with cadence 45-nm technology at the supply voltage of 1V. Index Terms: Matchline Structure, NOR type TCAM , Precharge, Ternary CAM. AUTHORS PROFILE Venkata Ramana Datti received theB.Tech. degree in electronics and communication engineeringfrom Acharya Nagarjuna University, Guntur, India, the M.Tech degree in VLSI System Design from JNTU Kakinada,India. He is currently pursuing the Ph.D. degree with the Andhra University college of Engineering(A),Andhra University, Visakhapatnam India .His current research interests include memorydesign, flip-flop design, and low-power VLSI design. P.V.Sridevi (M'10) received the B.Tech. degree in electronics and communication engineering From