Purpose Waste management for end-of-life (EoL) smartphones is a growing problem due to their high turnover rate and concentration of toxic chemicals. The versatility of modern smartphones presents an interesting alternative waste management strategy: repurposing. This paper investigates the environmental impact of smartphone repurposing as compared to traditional refurbishing using Life Cycle Assessment (LCA). Methods A case study of repurposing was conducted by creating a smartphone "app" that replicates the functionality of an in-car parking meter. The environmental impacts of this prototype were quantified using waste management LCA methodology. Studied systems included three waste management options: traditional refurbishment, repurposing using battery power, and repurposing using a portable solar charger. The functional unit was defined as the EoL management of a used smartphone. Consequential system expansion was employed to account for secondary functions provided; avoided impacts from displaced primary products were included. Impacts were calculated in five impact categories. Break-even displacement rates were calculated and sensitivity to standby power consumption were assessed.Results and discussion LCA results showed that refurbishing creates the highest environmental impacts of the three reuse routes in every impact category except ODP. High break-even displacement rates suggest that this finding is robust within a reasonable range of primary cell phone displacement. The repurposed smartphone in-car parking meter had lower impacts than the primary production parking meter. Impacts for battery-powered devices were dominated by use-phase charging electricity, whereas solar-power impacts were concentrated in manufacturing. Repurposed phones using battery power had lower impacts than those using solar power, however, standby power sensitivity analysis revealed that solar power is preferred if the battery charger is left plugged-in more than 20 % of the use period. Conclusions Our analysis concludes that repurposing represents an environmentally preferable EoL option to refurbishing for used smartphones. The results suggest two generalizable findings. First, primary product displacement is a major factor affecting whether any EoL strategy is environmentally beneficial. The benefit depends not only on what is displaced, but also on how much displacement occurs; in general, repurposing allows freedom to target reuse opportunities with high "displacement potential." Second, the notion that solar power is preferable to batteries is not always correct; here, the rank-order is sensitive to assumptions about user behavior.Keywords Avoided burden . End of life . E-waste . Reuse . Smartphone . System expansion . Waste management LCA IntroductionMillions of smartphones reach the end of their lives each year, making their responsible management an urgent environmental goal. Cell phone e-waste will continue to be a growing

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The basic building block of on-chip nanophotonic interconnects is the microring resonator [14], and these resonators change their resonant wavelengths due to variations in temperature -a problem that can be addressed using a technique called "trimming", which involves correcting the drift via heating and/or current injection. Thus far system researchers have modeled trimming as a per ring fixed cost. In this work we show that at the system level using a fixed cost model is inappropriate -our simulations demonstrate that the cost of heating has a non-linear relationship with the number of rings, and also that current injection can lead to thermal runaway. We show that a very narrow Temperature Control Window (TCW) must be maintained in order for the network to work as desired. However, by exploiting the group drift property of co-located rings, it is possible to create a sliding window scheme which can increase the TCW. We also show that partially athermal rings can alleviate but not eliminate the problem.

Abstract-Designers are increasingly relying on field-programmable gate array (FPGA)-based emulation to evaluate the performance of low-density parity-check (LDPC) codes empirically down to bit-error rates of 10 12 and below. This requires decoding architectures that can take advantage of the unique characteristics of a modern FPGA to maximize the decoding throughput. This paper presents two specific optimizations called vectorization and folding to take advantage of the configurable data-width and depth of embedded memory in an FPGA to improve the throughput of a decoder for quasi-cyclic LDPC codes. With folding it is shown that quasi-cyclic LDPC codes with a very large number of circulants can be implemented on FPGAs with a small number of embedded memory blocks. A synthesis tool called QCSyn is described, which takes the H matrix of a quasi-cyclic LDPC code and the resource characteristics of an FPGA and automatically synthesizes a vector or folded architecture that maximizes the decoding throughput for the code on the given FPGA by selecting the appropriate degree of folding and/or vectorization. This helps not only in reducing the design time to create a decoder but also in quickly retargeting the implementation to a different (perhaps new) FPGA or a different emulation board.Index Terms-Alignment, field programmable logic array (FPGA), folding, low-density parity-check (LDPC) decoder, memory system optimization, normalized min-sum algorithm, quasi-cyclic low-density parity-check (QC-LDPC) codes, very large scale integration (VLSI) implementation.

There is an increasing need for configurable quasicyclic low-density parity-check (QC-LDPC) decoders that can support a family of structurally compatible codes instead of a single code. The key component in a configurable QC-LDPC decoder is a programmable circular-shift network that supports cyclic shifts of any size up to a predefined maximum submatrix size. This paper presents a QC-LDPC shift network (QSN), which has two key advantages over state-of-the-art solutions in recent literature. First, the QSN reduces the number of stages in the critical path, which improves the clock frequency and makes it scalable, particularly in a field-programmable gate array (FPGA)-based implementation where an interconnect delay is dominant. Second, the QSN's control logic is simple to generate and occupies a significantly smaller area. The QSNs for a variety of codes suitable for emerging applications are implemented, targeting both a 180-nm Taiwan Semiconductor Manufacturing Company Ltd. complimentary metal-oxide-semiconductor library and a Xilinx Virtex 4 FPGA. The proposed implementation is shown to be 2.1 times faster than the best known implementation in literature and requires almost eight times less control area. Furthermore, this paper presents analytical models of the critical-path and datapath complexity for arbitrary-sized submatrices and proves that the QSN indeed generates all the output combinations required for implementing reconfigurable QC-LDPC decoders.