Two market trends that have been evident for some time are increasing microprocessor speeds and the increasing demand for additional functionality in electronic systems. These market trends in turn are driving the need for increased memory density and higher performance memory in systems such as personal computers, laptop computers and servers. To address these requirements, memory module manufacturers are looking to technologies capable of meeting these dual demands and at the same time keep overall costs trending down. New generations of dynamic random access memory (DRAM) such as Double Data Rate (DDR) and next generation DDR2 technologies are contributing significantly toward increased system performance. Several options, including Tessera's stacked chip scale packaging (CSP), have been developed to address these high density memory and performance requirements.Several critical issues surround this effort to increase the density and performance of electronic products. Form factor, electrical performance, thermal performance, reliability, cost and manufacturability. Future potential for higher density package technology will be outlined as it relates to trends in high density and high performance market needs. The following will examine the company's µZ™ Ball Stack package design, assembly methodology and performance requirements associated with Small-Outline, Dual-Inline Memory Module (SO-DIMM) applications and environmental stress test results for several µZ-Ball Stack package configurations. Market Drivers for Higher Density MemoryDemands for increased memory and miniaturization in electronics have led the packaging industry to develop a number of innovative solutions to meet these demands. The transition to CSP has already resulted in semiconductor packages being reduced to a size that is only slightly larger than the semiconductor chip. With the advent of 3D packaging, densification and miniaturization has now been taken to the next level offering solutions that utilize the vertical or 'Z' dimension to make better use of space that is available for component mounting. Target Applications for Higher Density Memory:• Dual In-line Memory Modules • Small Outline Memory Modules • Application Specific Memory • High-End Computing and Graphic Workstations • Ruggedized Hard Drives • MP3 Players and Cell Phones 3D Memory Package Performance CriteriaUntil recently, the component packaging industry did not directly concern itself about system level performance. This has increasingly becoming an issue and is evidenced by the restriction on the number of DIMM assemblies that can be designed onto the motherboard due to performance reasons. The first aspect of performance analysis is to characterize the performance of a single die Fine-pitch BGA (FBGA) package as a reference for comparing the Z-Ball Stack package performance. For this analysis, a DDR333 device in a single die FBGA package was used having a maximum inductance value of 3.188 nH and a value of capacitance 0.287 pF,. For an equivalent TSOP package, the value...

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To maximize the benefit of chip-scale packaging for portable and hand-held electronics, the user must consider efficient and cost effective assembly processing. Factors that an engineer should review before developing the product using CSP may include physical features and construction of the device, environmental limitations, suitable substrate materials and a general understanding attachment methodology. Many of the electronic products being developed using miniature chip-scale package are moving toward lead-free, environmentally safe assembly processes.This paper will review chip-size Flash and RAMBUS memory test device applications utilizing pBGAB package technology, explore alternative solder alloy compositions, furnish recommendations for solder process temperature profiles and present the results from extensive thermal cycle testing, comparing eutectic solder to lead-free solder ball contacts .and attachment materials. IntroductionIndustry specifications establish the specific test methods to evaluate the performance and reliability for CSP attachment. The tests are designed to replicate actual use environments of the electronic assemblies. In addition, it establishes different levels of performance and reliability of the solder attachments of all surface mount devices to rigid, flexible and rigid-flex circuit structures.

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BiographyVern Solberg has more than twenty-five years of experience in the design and manufacturing of electronic products. Founder of NuGrafix Group, the first design and engineering service company dedicated to SMT. He also served as Manager of Design Engineering for SCI Systems, a multinational assembly service company for eight years followed by five years as the Director of Advanced Manufacturing Technology with Tessera, the developer of the PBGA package technology. His primary activities are related to application engineering and assembly process development, serving as a technical advisor to in-house as well as OEM customer engineers and design specialists. Mr. Solberg is a member of IPC, IMAPS, and SMTA, focusing on product "Design for Manufacturing". AbstractA number of companies around the world are developing or have begun offering devices processed and packaged in the wafer format. Most of these competing concepts involve the creation of a redistribution layer over the face of the chip, a method long employed by IBM in the development of its well known flip-chip C4 processes. Wafer level packaging has the potential for transforming IC packaging from a labor ,intensive process of making wire bonds one-at-a-time on individual die, to a batch process, much like wafer fab. Tessera has developed a unique approach to wafer level packaging that provides a physically robust, compliant structure while offering significant cost reduction through a unique method of mass termination and encapsulation. In this paper, the authors will describe the materials and process developed for utilizing 'wide area vertical expansion' (WAVETM), producing what may prove to be the most reliable chip-size package available. To back-up this rather bold statement, the environmental test program description will be outlined and test data offered for review.