In this paper we discuss edge placement error (EPE) for multi-patterning application and compare the EPE budget with the one for EUV single expose application case. These two patterning methods are candidate for the manufacturing of 10-nm and 7-nm logic semiconductor devices. EUV will enable 2D random pattern layout, while in the multi-patterning case a more restricted 1D design layout is needed. For the 1D design approach we discuss the patterning control spacer pitch division resulting in complex multi-layer alignment and EPE optimization strategies. Solutions include overlay and CD metrology based on angle resolved scatterometry, scanner actuator control to enable high order overlay corrections and computational lithography optimization to minimize imaging induced pattern placement errors of devices and metrology targets. We use 10-nm node experimental data and extrapolate the error budgets towards the 7-nm technology node. The experimental data will be based on NXE:3300B and NXT:1960Bi/NXT:1970Ci exposure systems. The results are compared to the more straightforward alternative of using single expose patterning with EUV for all critical layers.

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For most applications of displays based on organic light‐emitting diodes (LEDs), it is desirable to have good daylight contrast in combination with a high intensity of emitted light. The conventional approaches to enhance the daylight contrast, using a black cathode or circular polarizers, result in a significant loss of light emitted by the LED. A rather novel approach to enhance daylight contrast while keeping loss of emitted light to a minimum is the introduction of a chiral‐nematic film in the device. This approach leads to an increase in light efficiency by a factor of 1.8 (with respect to circular polarizers) with some loss in daylight contrast values within the reflection band of the chiral‐nematic film. Outside the reflection band, however, the contrast approaches infinity.

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