Measured results of V MlN from 20nm SRAM array s with read and write assist techniques are presented for multiple flavors of bit cell. A novel assist technique is presented, that provides both read and write assist by controlling only the voltage of word line (WL) and without using a separate supply voltage. The WL-drivers use a WL float technique to reduce the dc-path current compared to existing WL under-drive read assist designs.The assist technique resulted in a VMlN improvement of 143mV for the high-density 6T (6T-HD) SRAM, 96mV for the high-speed 6T (6T-HS) SRAM, and 86mV for the 8T dual-port (DP) SRAM. I ntroductionThe traditional 6T SRAM is still the most attractive bitcell option as it offers the highest density, uses a single wordline, and generates differential bitlines. Unfortunately, operating SRAMs at lower voltages is becoming extremely challenging and requires several assist techniques to improve cell stability and writability and push the lowest voltage of operation (V MlN) [1]-[7]. This work presents a novel read and write assist (RWA) technique by controlling only the WL voltage and without using a separate supply voltage. The technique described in [4] is conceptually similar, but has significant timing penalty, especially for instances in worst case comer for read stability (FS: fast-N, slow-P) (Fig. 3). A novel WL float technique is used in this work that improves dc-path current over existing WL under-drive techniques [1],[2],[5],[7]. Measured results of VMlN from SRAM arrays built in 20nmbulk CMOS are presented. The arrays are built in a variety of sizes and using several bitcell options (6T-HD, 6T-HS, and DP). The SRAMs can be configured, using external pins, in the no-assist (NA) mode, the RWA mode or either of the read-assist only (RA) or write-assist only (WA) modes.These techniques are built as bolt-on options to the regular SRAM design to maximize design reuse and minimize design cycle time. Assist Techniques DesignThe assist circuitry and the simplified waveforms are shown in Fig.1 and Fig. 2 respectively. The read cycle of RW A mode consists of two intervals. In the first interval (TI), the WL is under-driven and is raised to a full VDD in the second interval (T2), alleviating the speed degradation due to the conventional WL under-drive [1][5]. The partial discharge of BL during TI results in a lowered read-bump during T2, and hence increases the read stability. The write cycle consists of 3 intervals. The first is identical to that of the read cycle and ensures that the half-selected bitcells (i.e., the non-accessed bitcel1s in the selected WL) are not read disturbed. The WL is raised to VDD in the second interval (T2) before providing it with a boost in the final interval. The boost strengthens the access devices and improves the chances to overcome the drive strength of the pull-up device within the cell, thus resulting in a successful write. The WL under-drive voltage is determined by the drive strength ratio of header PMOS (Pheader) and the footer device(s). The default footer...