Pedestrian detection is one of the key problems in the emerging self-driving car industry. In addition, the Histogram of Gradients (HOG) algorithm proved to provide good accuracy for pedestrian detection. Many research works focused on accelerating HOG algorithm on FPGA (Field-Programmable Gate Array) due to its low-power and high-throughput characteristics. In this paper, we present an energy-efficient HOG-based implementation for pedestrian detection system on a low-cost FPGA system-on-chip platform. The hardware accelerator implements the HOG computation and the Support Vector Machine classifier, the rest of the algorithm is mapped to software in the embedded processor. The hardware runs at 50 Mhz (lower frequency than previous works), thus achieving the best pixels processed per clock and the lower power design.

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After the first success with SigmaK3 [1], we have designed and developed the second 8-bit microprocessor chip, dubbed HN-07, with high performance and additional features. HN-07is based on the original Sigmak3 architecture with a number of improved features, namely 5-stage pipeline architecture, interrupt controller, more on-chip peripherals, higher operational stability and frequency. This improved architecture makes HN-07 microprocessor equivalent with others such as Intel 8051, Microchip PIC, etc. Our complete design, from front-end through back-end stages, has been taped out and supplied to an overseas foreign foundry for trial fabrication. Further detail on the evaluation of its performance will be reported in the future.

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