Abstract-Synthesizable all-digital analog-to-digital converters (ADCs) that can be designed, verified and taped out using a digital design flow are of interest due to a consequent reduction in design cost and an improved technology portability. As a step towards high performance synthesizable ADCs built using generic and low accuracy components, an ADC designed exclusively with standard digital cell library components is presented. The proposed design is a time-mode circuit employing a voltage controlled oscillator (VCO) based multi-bit quantizer. The ADC has first order noise-shaping due to inherent error feedback of the oscillator and sinc anti-aliasing filtering due to continuous-time sampling. The proposed architecture employs a Gray-counter based quantizer design, which mitigates the problem of partial sampling of digital data in multi-bit VCO-based quantizers. Furthermore, digital correction employing polynomial-fit nonlinearity estimation is proposed to correct for VCO non-linearity. The design occupies 0.026 mm 2 when fabricated in a 65 nm digital CMOS process and delivers an ENOB of 8.1 bits over a signal bandwidth of 25.6 MHz, while sampling at 205 MHz. The performance is comparable to that of recently reported custom designed single-ended open-loop VCO-based ADCs, while being designed exclusively with standard cells, and consuming relatively low average power of 3.3 mW achieving an FoM of 235 fJ/step.

True-time-delays enable wideband analog and hybrid beamforming by mitigating the beam squint problem. This paper reports a true-time-delay beamforming receiver supporting delays up to three carrier-frequency cycles. The implementation is the first published work in which the delays scale with the carrier frequency. The scaling enables true-time-delays for large arrays at low-GHz frequencies where long delays are required due to λc/2 antenna spacing. The delays are implemented through delayed resampling of a passive mixer's discrete-time output. Driving the mixers with pulse-skipped local oscillator (LO) signals allows the delay range to exceed one carrier cycle. A polyphase receiver structure prevents aliasing of noise and unwanted tones caused by LO pulse-skipping. Our prototype implementation demonstrates squint-free beamforming for an 800 MHz instantaneous RF bandwidth. The proposed true-timedelay is efficient for large arrays since the power consumption per antenna is only 5-13 mW across the 0.6-4.0 GHz frequency range. The prototype was implemented in 28-nm FD-SOI CMOS, and the die area including bonding pads is only 1.2 mm 2 .

Analog domain true-time-delays (TTD) are desired in hybrid beamforming receivers with large relative bandwidths to mitigate the problem of beam squint. We propose a true-timedelay beamforming receiver architecture which enables squintfree wideband spatial filtering prior to the A/D conversion. The receiver implements true-time-delay with delayed re-sampling of the discrete-time output of a passive mixer. The receiver has the capability to extend the range of the beamforming delays from one to several carrier periods of the RF signal with pulse-skipped local oscillator (LO) signals, thereby enabling TTD beamforming with large antenna arrays. Further, a polyphase structure with parallel mixers is proposed to prevent spectral aliasing resulting from the lowered sample rate of the pulse-skipped LO signals. In addition, the maximum beamforming delay scales with the LO frequency, supporting large arrays also at low frequencies where the antenna separation set by the wavelength is large. We verify the proposed concepts with transistor-level simulation of the receiver implemented with a 28-nm CMOS process. The design achieves a squint-free beamforming for a 400 MHz RF bandwidth, and a maximum beamforming delay of three carrier time periods. The power consumption for a 3 GHz carrier frequency is 4 mW per antenna.

Abstract-VCO-based ADC is a scaling-friendly architecture to build ADCs in fine-feature CMOS processes. Lending itself to an implementation with digital components, such a converter enables design automation with existing digital CAD hence reducing design and porting costs compared to a custom design flow. However, robust architectures and circuit techniques that reduce the dependence of performance on component accuracy are required to achieve good performance while designing converters with low accuracy components like standard cells in deeply-scaled processes. This work investigates errors resulting from sampling of a fast switching multi-phase ring oscillator output. A scheme employing ones-counters is proposed to encode the sampled ring oscillator code into a binary representation, which is resilient to a class of sampling induced errors modeled by temporal reordering of the transitions in the ring. In addition to correcting errors caused by deterministic reordering, proposed encoding suppresses conversion errors in the presence of arbitrary reordering patterns that may result from automatic place-and-route in wire-delay dominated processes. The error suppression capability of the encoding is demonstrated using MATLAB simulation. The proposed encoder reduces the error caused by random reordering of six subsequent bits in the sampled signal from 31 to 2 LSBs for a 31-stage oscillator.

An integrated circuit that measures time intervals with high precision and accuracy has a wide range of applications including data conversion, ranging, and 3D imaging. The resolution with which time intervals are quantized by a ring oscillator or delay line is limited by the minimum delay of an inverter in the technology. We propose the use of cycliccoupled ring oscillators as a time-domain quantizer to achieve a combination of sub-gate-delay time resolution together with a short conversion time, thereby enabling data conversion with high resolution as well as high bandwidth. The resolution-power trade-off in coupled oscillators is studied. Simulation indicates up to a factor-of-13 sub-gate-delay time resolution with 13 coupled oscillators. A real-time quantizing time-to-digital converter with coupled oscillators is designed for a time-domain analog-to-digital converter. Powered by a factor-of-8 sub-gate-delay time resolution of 1.6 ps obtained with nine coupled oscillators, and a sample time of 4 ns for 11-bit conversion, the converter delivers a 9.9-bit ENOB over a signal bandwidth of 125 MHz and an SFDR of 88 dB. Results demonstrate that cyclic-coupled ring oscillators is an attractive candidate as a high-precision high-linearity timedomain quantizer for data converters.