In many digital image-processingapplications, which are implementedin field programmable gate arrays,the currently processed image's frames are stored in external dynamic memory.The performance of such an application dependson the dynamic memoryspeed and the necessaryrequests quantity during algorithm’sruntime. This performance is being optimized through field programmable gate arrays -implemented buffer memory usage.But there is no common method for the formal buffer memory synthesis with preset throughput, input and output data sequenceorderand minimizedhardwarecosts.In this article,the featuresof image input and processing based on Field Programmable Gate Arrayareconsidered.The methods of building buffer circuits in field programmable gate arrays, due to which the intensity of data exchanges with external memory is reduced, are analyzed. Themethod of synthesizing pipeline circuits with specified performance characteristics and the data sequence order is given, which is based on the mapping of the spatial synchronous data flows into the structure implemented in the field programmable gate arrays.A method of designing buffer schemes is proposed, which is based on the mapping of spatial synchronous data flows into local memory in the form of chains of pipeline registers.The method helpsto organize the data flow of at the input of built-in pipeline units of image processing, in which the data follow in a given order, andto minimize the amount of buffer memory.The method ensures the use of dynamically adjustable register delays built into the field programmable gate arrays, which increases the efficiency of buffering.Thismethod was tested during the development of an intelligent video camera. The embedded hardware implements a video image compression algorithm with a wide dynamic range according to the Retinexalgorithm. The same time it selects characteristic points in the image for the further pattern recognition.At the same time, multiple decimation of the frame is performed. Due to themultirate buffering of the image in the field programmable gate arrays,it was possible to avoid using of external dynamic memory