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In the recent year tools for DFM (Design for Manufacturing) addressing the lithographic pattern transfer like LfD have evolved besides OPC (Optical Proximity Correction) to reduce the time required from design to manufacturing along the design to mask data preparation flow. The insertion of ORC (Optical Rule Check) after OPC in a separate mask data preparation step has been commonly adopted in order to successfully meet the ever increasing need of an advanced technology node like 130nm, 90nm, 65nm and below. Separate simulation runs are normally done for both OPC and ORC and it is not unusual that different platforms (software, hardware or algorithm) are used for OPC and ORC, especially for better ORC processing throughput. An investigation has been made to look into the possibility of a DFMlite approach by inserting ORC into the OPC run on the same Calibre platform. This is accomplished by adding additional intelligence necessary to provide a 'polishing' step for a hotspot identified, without increasing the combined cycle time but having the benefit of both full OPC and partial ORC in a single simulation run.

In today's semiconductor industry downscaling of the IC design puts a stringent requirement on pattern overlay control. Tighter overlay requirements lead to exceedingly higher rework rates, meaning additional costs to manufacturing. Better alignment control became a target of engineering efforts to decrease rework rate for high-end technologies.Overlay performance is influenced by known parameters such as "Shift, Scaling, Rotation, etc", and unknown parameters defined as "Process Induced Variation", which are difficult to control by means of a process automation system. In reality, this process-induced variation leads to a strong wafer to wafer, or lot to lot variation, which are not easy to detect in the mass-production environment which uses sampling overlay measurements for only several wafers in a lot. An engineering task of finding and correcting a root cause for Process Induced Variations of overlay performance will be greatly simplified if the unknown parameters could be tracked for each wafer.This paper introduces an alignment performance monitoring method based on analysis of automatically generated "AWE" files for ASML scanner systems. Because "AWE" files include alignment results for each aligned wafer, it is possible to use them for monitoring, controlling and correcting the causes of "process induced" overlay performance without requiring extra measurement time. Since "AWE" files include alignment information for different alignment marks, it is also possible to select and optimize the best alignment recipe for each alignment strategy. Several case studies provided in our paper will demonstrate how AWE file analysis can be used to assist engineer in interpreting pattern alignment data.Since implementing our alignment data monitoring method, we were able to achieve significant improvement of alignment and overlay performance without additional overlay measurement time. We also noticed that the rework rate coming from alignment went down and stabilized at quite satisfactory level.

We report a non-destructive in-line monitoring method developed for Cd diffusion into InP on SACM-APD structure. Photocurrent vs voltage measurements are taken directly via probing diffused diodes on a wafer. We demonstrate that there is linear correlation between punch-through voltages Vpt on the photo I-V curves and diffusion depth measured by SIMS and Polaron profiles. It has been established that Vpt can be extracted easily from I-V curves and used for re-diffusion to approach target depth.