An enhancement mode PHEMT MMIC with integrated dual low noise amplifiers, dual switches, and dual distortion compensation power amplifiers is presented. It is used in an 802.11abgn FEM (Front End Module) which further integrates the antenna diplexer, LNA post filters, PA pre-filters, and baluns. The LNAs provide less than 1.2dB noise figure in the 2.4/5-6GHz receive chains at 16dB gain and 10mA. The switches can handle up to 30dBm peak power with less than 1.4dB loss and with 25dB isolation. The power amplifier section provides fully matched 26dB gain with 25dBm of saturated power. In the 802.11g 2.4GHz transmit mode the MMIC gives over 20dBm linear power out under 54Mbps OFDM, at 4% EVM, while drawing only 123mA of peak current. In the 802.11a 5-6 GHz transmit mode the MMIC gives over 20dBm linear power out under 54 Mbps OFDM, at 6% EVM while drawing 149mA of peak current. The MMIC has integrated all control functions for power down and mode select; while the power amplifiers have integrated directional couplers and temperature compensated power detection. This is the highest integration and performance level combination known to be published for 802.11abgn application specific integrated circuits.
An enhancement-mode three stage GaAs FET power MMIC has been developed for single supply portable applications. The MMIC operates fkom a 4.8V power supply and provides over 35 dBm output power from 890-915 MHz with more than 35 dB gain and 47% power added efficiency. Power control range is greater than 70dB. Leakage current is 2uA.
Large Signal S parameters have been measured up to 12 GHz on high power (6W) 18" gate width FET chips. The unique feature of this method is its ability to measure both forward (Sll,S21) as well as reverse (S12,S22) parameters while the chip is operating under high power levels. The paper describes an approach that deals with extremely low impedance levels (0.5 ohm or VSWRs >90:1). The test setup employs HP8510CThe well known approaches to the large signal characterization are the load pull and the source pull techniques. These techniques provide only load and source match information. They fall short in providing full S-parameters, particularly that of S12 which is critical in the design of high frequency multistage module designs. Further, the commercially available load pull systems can only operate over VSWRs less than lO:l, while most large Power FET chips under consideration present VSWRs greater than 90: 1.
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