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High-κ dielectric stacks have been used to replace the conventional SiO 2 -based dielectric stacks in Flash memory cells in the 20 nm technology generation. The electron trap density in high-κ layers is orders of magnitude higher than that in SiO 2 , which introduces fast transient trapping/detrapping and affects the program/erase, retention and endurance of memory cells. Several fast pulse techniques have been developed to characterize electron traps throughout the dielectric stack, including 2-pulse and multi-pulse C-V and I-V techniques. These techniques are compared in this work and electron trapping in the high-κ stacks and its impact on memory cell performances are evaluated using these techniques.

As device sizes scale down, device variations scale up. There are two types of device-to-device variations (DDV): as-fabricated or time-zero DDV and the time dependent variations (TDV). Even if two nano-scaled devices were identical at time-zero, they would be different after stresses and result in TDV, since the defect generation and charging-discharging are stochastic. To characterize TDV, statistical properties, such as the mean value and standard deviation, are extracted from tests. Their accuracy improves as the number of device under tests (DUTs) increases. Ageing is time consuming and the typical DUTs used are in the range of tens to hundreds. There is little information on the accuracy of the statistical properties extracted from such a limited DUTs and the objective of this paper is to propose a methodology to assess it. Based on the defect-centric model, the accuracy with a specific confidence level is evaluated for a given number of DUTs and a stress level.