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This paper describes a hardware-software co-design approach for flexible programmable Galois Field Processing for applications which require operations over GF(2 m ), such as RS and BCH codes, Elliptic Curve Cryptography and the AES. Complexities of flexible implementations of different applications on a same computation architecture can be migrated to software during design time. However, the underlying GF(2 m ) arithmetic architecture needs to be designed with software programmability (or reconfigurability) in mind. We describe novel reconfigurable subword parallel GF(2 m ) arithmetic architectures designed with an associated instruction set architecture for different applications over GF(2 m ) and same applications with differing parameters. Design space exploration is carried out with two simple parameters P and Q which can be changed at design time and will affect the performance of different applications and flexibility of the final implementation. We show implementation results given for an FPGA prototype of the processor and programmed for RS and BCH coding, AES and elliptic curve cryptography with differing parameters. Complexity figures and configuration overheads for subword parallel GF(2 m ) arithmetic architectures are also estimated and discussed.

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