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Bulk syntheses of colloids efficiently produce nanoparticles with unique and useful properties. Their integration onto surfaces is a prerequisite for exploiting these properties in practice. Ideally, the integration would be compatible with a variety of surfaces and particles, while also enabling the fabrication of large areas and arbitrarily high-accuracy patterns. Whereas printing routinely meets these demands at larger length scales, we have developed a novel printing process that enables positioning of sub-100-nm particles individually with high placement accuracy. A colloidal suspension is inked directly onto printing plates, whose wetting properties and geometry ensure that the nanoparticles only fill predefined topographical features. The dry particle assembly is subsequently printed from the plate onto plain substrates through tailored adhesion. We demonstrate that the process can create a variety of particle arrangements including lines, arrays and bitmaps, while preserving the catalytic and optical activity of the individual nanoparticles.

Universal fault-tolerant quantum computers will require error-free execution of long sequences of quantum gate operations, which is expected to involve millions of physical qubits. Before the full power of such machines will be available, near-term quantum devices will provide several hundred qubits and limited error correction. Still, there is a realistic prospect to run useful algorithms within the limited circuit depth of such devices. Particularly promising are optimization algorithms that follow a hybrid approach: the aim is to steer a highly entangled state on a quantum system to a target state that minimizes a cost function via variation of some gate parameters. This variational approach can be used both for classical optimization problems as well as for problems in quantum chemistry. The challenge is to converge to the target state given the limited coherence time and connectivity of the qubits. In this context, the quantum volume as a metric to compare the power of near-term quantum devices is discussed.With focus on chemistry applications, a general description of variational algorithms is provided and the mapping from fermions to qubits is explained. Coupledcluster and heuristic trial wave-functions are considered for efficiently finding molecular ground states. Furthermore, simple error-mitigation schemes are introduced that could improve the accuracy of determining ground-state energies. Advancing these techniques may lead to near-term demonstrations of useful quantum computation with systems containing several hundred qubits.PACS numbers: quantum computation, quantum chemistry, quantum algorithms

The operation of electronic devices relies on the density of free charge carriers available in the semiconductor; in most semiconductor devices this density is controlled by the addition of doping atoms. As dimensions are scaled down to achieve economic and performance benefits, the presence of interfaces and materials adjacent to the semiconductor will become more important and will eventually completely determine the electronic properties of the device. To sustain further improvements in performance, novel field-effect transistor architectures, such as FinFETs and nanowire field-effect transistors, have been proposed as replacements for the planar devices used today, and also for applications in biosensing and power generation. The successful operation of such devices will depend on our ability to precisely control the location and number of active impurity atoms in the host semiconductor during the fabrication process. Here, we demonstrate that the free carrier density in semiconductor nanowires is dependent on the size of the nanowires. By measuring the electrical conduction of doped silicon nanowires as a function of nanowire radius, temperature and dielectric surrounding, we show that the donor ionization energy increases with decreasing nanowire radius, and that it profoundly modifies the attainable free carrier density at values of the radius much larger than those at which quantum and dopant surface segregation effects set in. At a nanowire radius of 15 nm the carrier density is already 50% lower than in bulk silicon due to the dielectric mismatch between the conducting channel and its surroundings.

A generic process for fabricating vertical surround‐gate field‐effect transistors (FETs) from epitaxially grown silicon nanowires is presented. The process is demonstrated using n‐type Si nanowires grown on a p‐type substrate in ultrahigh vacuum using a Au catalyst. The process consists of various deposition and etching steps; no chemical or mechanical polishing is required. Individual as well as arrays of vertical surround‐gate FETs can be fabricated.