Realization of a Silicon Nanowire Vertical Surround‐Gate Field‐Effect Transistor

Schmidt, Volker; Riel, Heike; Senz, Stephan; Karg, Siegfried; Rieß, W.; Gösele, U.

doi:10.1002/smll.200500181

Cited by 369 publications

(260 citation statements)

References 19 publications

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“…Higher performance FETs could come from Silicon nanowires, which are fairly easy to grow and have properties that can be used in transistors (Schmidt et al 2006;Yoon et al 2006), and Carbon nanotubes, which are also commonly available and can make transistors (Martel et al 2001;Chen et al 2008). Assembly of these nanoscale objects into useful circuitry is a challenge.…”

Section: New Transistor Technologymentioning

confidence: 99%

Future Trends in Computing

Elmegreen¹

2010

Proc. IAU

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Abstract. According to a Top500.org compilation, large computer systems have been doubling in sustained speed every 1.14 years for the last 17 years. If this rapid growth continues, we will have computers by 2020 that can execute an Exaflop (10 18 ) per second. Storage is also improving in cost and density at an exponential rate. Several innovations that will accompany this growth are reviewed here, including shrinkage of basic circuit components on Silicon, three-dimensional integration, and Phase Change Memory. Further growth will require new technologies, most notably those surrounding the basic building block of computers, the Field Effect Transistor. Implications of these changes for the types of problems that can be solved are briefly discussed.

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Section: New Transistor Technologymentioning

confidence: 99%

Future Trends in Computing

Elmegreen¹

2010

Proc. IAU

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“…Suk et al have shown transistor data for 10-nm lateral Si wires with a full wrap gate using SiO 2 as gate dielectric [3]. In the vertical geometry, many groups are currently working with epitaxially grown nanowires [4]- [7]. An important motivation here is the possibility of growing group III-V nanowires directly on Si, as well as highly lattice-mismatched semiconductor heterostructures within a wire [8]- [10].…”

mentioning

confidence: 99%

Vertical Enhancement-Mode InAs Nanowire Field-Effect Transistor With 50-nm Wrap Gate

Thelander

FrobergFroberg

Rehnstedt

et al. 2008

IEEE Electron Device Lett.

174

108

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Abstract-We present results on fabrication and dc characterization of vertical InAs nanowire wrap-gate field-effect transistor arrays with a gate length of 50 nm. The wrap gate is defined by evaporation of 50-nm Cr onto a 10-nm-thick HfO 2 gate dielectric, where the gate is also separated from the source contact with a 100-nm SiO x spacer layer. For a drain voltage of 0.5 V, we observe a normalized transconductance of 0.5 S/mm, a subthreshold slope around 90 mV/dec, and a threshold voltage just above 0 V. The highest observed normalized on current is 0.2 A/mm, with an off current of 0.2 mA/mm. These devices show a considerable improvement compared to previously reported vertical InAs devices with SiN x gate dielectrics.

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“…In principle, similar fabrication schemes can be used with other nanowire/substrate combinations. Similar strategy has been employed for the realization of a VSG-FET using Si nanowire grown epitaxially by CVD on a (111)-oriented p-type Si substrate (Schmidt et al, 2006). The surround gate allows better electrostatic gate control of the conducting channel and offers the potential to drive more current per device area than is possible in a conventional planar architecture (Wang et al, 2004).…”

Section: Patterned Growth Of Vertical Nanowiresmentioning

confidence: 99%