A method for fabricating a Si-based packaging platform with a reflector and electrode-guided interconnections is proposed for the packaging component of a high-power light-emitting diode (LED) module. The reflector is fabricated by Ni/Au/Ag-electroplating which is patterned by SU-8 2075 and 4620 negative photo-resistors and the electrical interconnections are formed by Cu/Au-electroplating in the same body. The heat generated by the LED chip is dissipated directly to the Si body through the large metal-plated platform. This method is suitable for high-efficiency and low-cost LED packaging.Introduction: In recent years the use of GaN-based LEDs for solid-state lighting has increased tremendously owing to their long guaranteed lifetime, low power consumption, high brightness, low cost, and little harmfulness. To this end, high-power LEDs are expected to replace traditional incandescent bulbs and fluorescent lights in many application areas such as household illumination, automotive lights, backlight units, and traffic signals [1]. However, for these near-future applications, cost and thermal design are the key parameters in high-power LED package design. The design of good packaging by using proper materials and structures is important to ensure both the thermal and the mechanical reliabilities of LED packages. With the improvement in LED packaging, several packaging methods for improving high-power LED performance have been presented [2, 3]. However, these methods need more complicated fabrication processes and come at higher cost. In this Letter we propose a method for packaging high-power LEDs that uses Si substrate and electroplating technology. A reflector and electrode-guided interconnections are integrated in one packaging body with excellent mechanical stability and heat dissipation. The packaging body is composed of Si substrate, Cu and Au, all of which have excellent thermal conductivities. The thermal conductivities (at 300 K) are 148, 401 and 317 W . m 21 . K 21 , respectively. An undoped Si wafer is used as a packaging substrate and electroplated Cu/Au with patterns of electrode for the electrical interconnection. The SU-8 barrier formed between the connection plates provides electrical isolation and a protective passivation layer for the ground metal pad. The reflector is formed by Ni/Au/Ag electroplating with an angle of 608 -708, which is patterned by SU-8 2075 and 4620 photo-resistors (PRs). The heat generated by the LED will be directly dissipated through the large Cu-plated platform to the whole body of the Si substrate and the light emitted from the LED can be reflected by the reflector. The LED chip will be connected with the Zener diode and covered with fluorescent material and accommodated inside the reflector by wire-bonding. The lens will be built up by injecting epoxy in the form of a dome.

A physical dicing method for realising backside source grounding is first proposed for high-power microwave AlGaN/GaN high electron mobility transistors (HEMTs) on 4-inch 477 mm-thick silicon carbide (SiC) substrates. The successful implementation of the dicing-assisted source grounding technology in the processing of HEMTs is confirmed by DC and RF characterisation. When biased at 30 V, a 10 GHz output power density of 9.18 W/mm is achieved with an associated gain of 9.6 dB and power added efficiency of 50% for a 2 × (200 × 0.5) mm 2 AlGaN/GaN HEMT with backside source grounding.Introduction: In recent years, the use of AlGaN/GaN HEMTs for microwave power devices has attracted much attention, owing to their high-frequency power handling capability, wide bandgap, high breakdown voltage, high current density, and high saturation velocity [1]. Silicon carbide (SiC) substrates are presently the best choice of high-performance AlGaN/GaN HEMT structures for epitaxial growth, owing to their excellent crystal quality with good thermal conductivity [2]. Source grounding is a key technology in realising AlGaN/GaN HEMT MMICs for high-power amplifiers. The source wire-bonding scheme is obviously not a good solution because it reduces the device characteristics owing to the increase of the specific on-resistance [3], making the fabrication of the device complex, reducing the reliability, and expanding their area. To analyse the above-mentioned problems, a through-wafer via connection is required. However, there is no feasible technology known for processing vias through 477 mm-thick chemically inert and very hard SiC. The formation of via holes using metal mask and plasma processing requires time-consuming preparation, owing to the low SiC etching rate of ≤2 mm/min, even in the case of advanced inductively coupled plasma (ICP) etching [4]. In this Letter, we propose a physical dicing method for realising the source grounding, instead of the conventional plasma-based via, on 477 mm-thick SiC substrates, which would allow simplified device mounting and space-saving design strategies. Neither a time-consuming ICP etching process nor backside lithography is necessary to realise the source grounding.