The accelerated degradation phenomena in amorphous silicon thin film transistors due to both electrical stress and visible light illumination under the elevated temperature have been investigated systematically as a function of gate bias, light intensity, and stress time. It has been found that, in case of electrical stress, the threshold voltage shifts of a-Si TFT's may be attributed to the defect creation process at the early stage, while the charge trapping phenomena may be dominant when the illumination periods exceed about 2 hours. It has been also observed that the degradation in the device characteristics of a-Si TFT's is accelerated due to multiple stress effects, where the defect creation mechanism may be more responsible for the degradation rather than the charge trapping mechanism.

The asymmetric amorphous silicon thin film transistors are fabricated and exposed to various stress environments. A visible light illumination of 200,000 Ix and gate bias of 30 V are applied to both asymmetric and widely used symmetric a-Si TFT's. It is observed that the leakage current of asymmetric structure, where only one electrode is fully overlapped by gate electrode, is much less than that of symmetric one. The visible light illumination as well as gate bias stress do not degrade the leakage current of the asymmetric a-Si TFT's, while the leakage current in die symmetric TFT's are increased considerably due to the stress. Also, the degree of degradation in the threshold voltage, the field effect mobility and the subthreshold slope of asymmetric TFT's are relatively much less than that of conventional symmetric TFT's.