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This paper describes the lessons learnt during the development and testing of the Modular Architecture for Robust Computing (MARC) demonstration system. It is principally written from a hardware perspective.The MARC system is designed for satellite avionics applications. The network and power architectures are based on established spacecraft redundancy concepts and provide tolerance to single point failures. The MARC architecture is designed to provide a scalable solution that can meet the demanding needs of future missions, the SpaceWire network can be expanded to include new functions and to provide duplicate paths to achieve the level of redundancy needed for a particular mission.An important aspect of the demonstrator hardware is that the key components are space qualifiable parts; permitting the design to be upgraded to a fully space qualified system with minimal changes, in particular the hardware design uses the ESA Atmel AT697F processor and SpaceWire 10X router developments. The ESA SpaceWire RMAP IP Core is also used for all module network interfaces, being implemented within FPGAs.The lessons learnt include the experiences with implementing the RMAP IP Core, VHDL synthesis problems, power consumption issues and the need for detailed internal unit interface specifications. Additional technology developments, such as radiation and fault tolerant Point of Load converters that are required for migration of the design to flight are also identified.Lessons were also learnt regarding parallel Hardware and Software developments to reduce development timescales whilst eliminating diverging design compatibility.

CCD and APS devices are widely used in space missions as instrument sensors and/or in Avionics units like star detectors/trackers. Therefore, various and numerous designs of video acquisition chains have been produced.

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