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Obstacle-avoiding rectilinear Steiner minimal tree (OARSMT) construction is becoming one of the most sought after problems in modern design flow. In this paper we present FOARS, an algorithm to route a multi-terminal net in the presence of obstacles. FOARS is a top down approach which includes partitioning the initial solution into subproblems and using obstacle aware version of Fast Lookup Table based Wirelength Estimation (OA-FLUTE) at a lower level to generate an OAST followed by recombining them with some backend refinement. To construct an initial connectivity graph FOARS uses a novel obstacle-avoiding spanning graph (OASG) algorithm which is a generalization of Zhou's spanning graph algorithm without obstacle [1]. FOARS has a run time complexity of O(n log n). Our experimental results indicate that it outperforms Lin et al. [2] by 2.3% in wirelength. FOARS also has 20% faster run time as compared with Long et al. [3], which is the fastest solution till date.

We propose a power-driven flip-flop merging and relocation approach that can be applied after conventional timingdriven placement and before clock network synthesis. It targets to reduce the clock network size and thus the clock power consumption, as well as the switching power of the nets connected to the flip-flops by selectively merging flipflops into multi-bit flip-flops and relocating them under timing and placement density constraints. The experimental results are very encouraging. For a set of benchmarks, our approach reduced the clock wirelength by 30 to 50%. Meanwhile, the switching power of signal nets connected to the flip-flops were reduced by 2 to 43%.

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