This paper describes implementation of an offset quadrature phase shift keying (OQPSK)-pulse-shaping block as a part of digital transmitter. The implementation is based on 2.4 GHz-band IEEE 802.15.4 standard. In this paper, the implementation results are compared to the results of OQPSK modulator and pulse-shaping block in terms of simulation waveform, design size, and synthesis run time. These blocks were designed using Verilog code through Xilinx ISE as a new design method and been implemented on Spartan3E XC3S500E field programmable gate array (FPGA). Current review shows that configurations for the implementation of OQPSK-pulse-shaping block, require 26.4% slices, 22.9% sliced flip-flops, and 15.5% look-up tables (LUTs), which is much better than the results of OQPSK modulator and pulseshaping block. At clock frequencies of 2 MHz and 25 MHz, the synthesis run time for OQPSK-pulse-shaping block shows substantial improvement with 48 ns faster than the two blocks.

Abstract:In the current paper, an improvement of piecewise curvature-corrected CMOS bandgap reference (BGR) circuit is proposed. The circuit utilizes piecewise nonlinear curvature-corrected current (PNCCC) in a conventional BGR with a current control circuit, which compensates for the voltage reference at a higher temperature range. The current control circuit (CCC) is used to reduce the total current at low temperature when the PNCCC generator is inactive. The proposed circuit is realized in CMOS 0.13 µm and has been verified to be able to save power consumption by 18.6% compared with a circuit without the current control circuit.