Wideband power amplifiers (PAs) with high power-added efficiency (PAE) are required by software-defined radio and high-data-rate communications. A PA in Class-AB, which can provide linear amplification with PAE better than Class-A, has been reported in [1] to achieve bandwidth larger than one octave. However, Class-AB operation generates a large amount of 2 nd -harmonic current at the transistor output, which has amplitude as high as up to 42% of the fundamental current in theory [2]. An output matching network, providing optimum load impedance only at the fundamental frequency, is insufficient to achieve good power performance, bringing big challenges to integrated Class-AB PA design with octave bandwidth. In this work, we demonstrate a 2-to-6GHz (fractional bandwidth of 115.5%) Class-AB PA designed in 65nm CMOS. An output matching technique based on differential architecture, which enables the PA to achieve a maximum PAE of 28.4% and an overall PAE above 19%, is proposed to provide transistor output with optimum load impedance for both fundamental and 2 nd harmonic over an octave bandwidth. Without using any pre-distortion, the PA can deliver output power of 9.31 to 11.31dBm with EVM<-32dB for 256QAM signal (802.11ac format, 20MHz bandwidth) from 2 to 6GHz. Figure 2.5.1 shows the schematic of the proposed PA.To design the output matching network, optimum load impedances for fundamental (Z opt_1st ) and 2 nd -harmonic (Z opt_2nd ) frequencies of the output stage are simulated from 2 to 6GHz. A model composed of parallel R out and C out (27Ω and 0.94pF for the given device) showing good agreement with Z opt_1st over the bandwidth is built for synthesizing the matching network for the fundamental frequency. With Z opt_1st set at the fundamental frequency, simulated contours of P SAT and PAE at representative frequencies of 2.4, 3.7 and 5.8GHz for load impedance at the 2 nd harmonic are shown in Fig. 2.5.2, where impedances on the Smith chart are normalized to R out . It shows that even with the fundamental frequency optimally matched, load impedance at the 2 nd harmonic may vary P SAT and PAE by 4.56/4.07/3.58dB and 29.6%/26.1%/21.1% respectively. Considering the susceptance of C out , target areas of 2 nd -harmonic impedance on the Smith chart indicate that impedance close to a short circuit, or capacitive impedance with normalized amplitude smaller than 1, is required at the current source reference plane of the transistor output to achieve good P SAT and PAE.To make the matching of the fundamental and 2 nd harmonic over an octave possible, differential architecture is adopted such that fundamental currents at the transistor output are in differential mode but 2 nd -harmonic currents are in common mode. By utilizing the coupling inside the transformer primary winding and the different behaviours of the transformer center-tap under the two modes, the output matching network providing Z opt_1st and Z opt_2nd with bandwidth larger than one octave can be designed. As shown in Fig. 2.5.1, the two halves of the transf...

No abstract

A low voltage low power highly linear CMOS quadrature mixer using transconductance cancellation technique Yeo,

No abstract

This paper presents our developed two-chip wireless communication system adhering to the IEEE S02.Had standards with a baseband IC (BBIC) integrated with a low power 60 GHz transceiver SOC (RFIC) and antennas. The novel low power 60GHz RFIC using a sub-harmonic sliding-IF scheme is fully integrated based on low cost SiGe O.IS urn BiCMOS process. The BBIC uses an adaptive time domain equalizer rather than the commonly used frequency domain equalizer to lower the requirements on power consumption.