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This paper describes a 10-bit, 50-MS/s pipelined A/D converter (ADC) with proposed area-and powerefficient architecture. The conventional dedicated sample-hold-amplifier (SHA) is eliminated and the matching requirement between the first multiplying digital-to-analog converter (MDAC) and sub-ADC is also avoided by using the SHA merged with the first MDAC (SMDAC) architecture, which features low power and stabilization. Further reduction of power and area is achieved by sharing an opamp between two successive pipelined stages, in which the effect of opamp offset and crosstalk between stages is decreased. So the 10-bit pipelined ADC is realized using just four opamps. The ADC demonstrates a maximum signal-to-noise distortion ratio and spurious free dynamic range of 52.67 dB and 59.44 dB, respectively, with a Nyquist input at full sampling rate. Constant dynamic performance for input frequencies up to 49.7 MHz, which is the twofold Nyquist rate, is achieved at 50 MS/s. The ADC prototype only occupies an active area of 1.81 mm 2 in a 0.35 m CMOS process, and consumes 133 mW when sampling at 50 MHz from a 3.3-V power supply.

A low power, highly linear active-RC filter is presented. This filter is synthesized from a low pass 6 order Chebyshev RLC ladder, and exhibits a reconfigurable bandwidth (10 MHz, 50 MHz). In order to meet the high cutoff frequency (50 MHz) and strict adjacent channel rejection requirements, a novel operational amplifier based on a new compensation technique is used, which optimizes high frequency filter performance and minimizes current consumption. This filter is fabricated in a 0.18 m CMOS process, the measurement results indicate that the filter provides 10 MHz and 50 MHz selectable bandwidth, and excellent adjacent channel rejection: -15.3 dB at 12.5 MHz with 10 MHz cutoff frequency, -8.3 dB at 60 MHz with 50 MHz cutoff frequency, three times out-band rejection more than 60 dB while the in-band ripple is less than 1 dB.