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This paper presents a boundary scan test solution for three-dimensional (3D) heterogeneous system integration platform, namely, MorPACK (morphing package). The 3D-stacking technique makes the MorPACK platform with heterogeneous integration capabilities through connection modules and circuit modules. The architecture of MorPACK platform achieves high performance and function flexibility with low silicon area cost by sharing the MorPACK common system platform (CSP) on heterogeneous system integration. In order to verify the function of MorPACK platform, the interconnection wire is a critical component between circuit modules and connection modules on PCB board. The boundary scan test is used to check the correctness of interconnection wire on PCB board and then achieves high fault coverage and high quality. The simulation results show that the proposed boundary scan test solution is slightly increased in area and timing of ARM CPU with 1.4% and 1.9% respectively. The south-bridge only consumes the area plenty with 4.5%. Therefore, the proposed method can arrange the routing of PCB board to achieve the verification of interconnection wire and then obtains the small area cost without addressable scan port chip.

The present SoC prototyping platforms in the market are usually with stationary connecting architecture, including designated bus protocols and peripheral interfaces. Due to the lack of architectural flexibility, users are not allowed to adapt the architecture for specific applications by on-chip-buses and on-chip-networks. In addition, the system architecture under the FPGA-based SoC may differ from the real chip. In our previous work, a configurable SoC prototyping platform, namely, CONCORD, was proposed to provide high flexibility, compatibility, and modularity in connection interfaces, for demands from various applications. In this paper, an improved version, named CONCORD II, is proposed. In contrast to CONCORD, CONCORD II operates with higher clock rate, greater FPGA capacity, more types of transmission signals, and additional categories of peripheral sub-modules.