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Enhanced disease susceptibility1 (EDS1) and phytoalexin deficient4 (PAD4) are well-known regulators of both basal and resistance (R) protein-mediated plant defense. We identified two EDS1-like (GmEDS1a/GmEDS1b) proteins and one PAD4-like (GmPAD4) protein that are required for resistance signaling in soybean (Glycine max). Consistent with their significant structural conservation to Arabidopsis (Arabidopsis thaliana) counterparts, constitutive expression of GmEDS1 or GmPAD4 complemented the pathogen resistance defects of Arabidopsis eds1 and pad4 mutants, respectively. Interestingly, however, the GmEDS1 and GmPAD4 did not complement pathogen-inducible salicylic acid accumulation in the eds1/pad4 mutants. Furthermore, the GmEDS1a/GmEDS1b proteins were unable to complement the turnip crinkle virus coat protein-mediated activation of the Arabidopsis R protein Hypersensitive reaction to Turnip crinkle virus (HRT), even though both interacted with HRT. Silencing GmEDS1a/GmEDS1b or GmPAD4 reduced basal and pathogen-inducible salicylic acid accumulation and enhanced soybean susceptibility to virulent pathogens. The GmEDS1a/GmEDS1b and GmPAD4 genes were also required for Resistance to Pseudomonas syringae pv glycinea2 (Rpg2)-mediated resistance to Pseudomonas syringae. Notably, the GmEDS1a/GmEDS1b proteins interacted with the cognate bacterial effector AvrA1 and were required for its virulence function in rpg2 plants. Together, these results show that despite significant structural similarities, conserved defense signaling components from diverse plants can differ in their functionalities. In addition, we demonstrate a role for GmEDS1 in regulating the virulence function of a bacterial effector.

Abstract-With the rapid increase of complexity in Systemon-a-Chip (SoC) design, the electronic design automation (EDA) community is moving from RTL (Register Transfer Level) synthesis to behavioral-level and system-level synthesis. The needs of system-level verification and software/hardware codesign also prefer behavior-level executable specifications, such as C or SystemC. In this paper we present the platform-based synthesis system, named xPilot, being developed at UCLA. The first objective of xPilot is to provide novel behavioral synthesis capability for automatically generating efficient RTL code from a C or SystemC description for a given system platform and optimizing the logic, interconnects, performance, and power simultaneously. The second objective of xPilot is to provide a platform-based system-level synthesis capability, including both synthesis for application-specific configurable processors and heterogeneous multi-core systems. Preliminary experiments on FPGAs demonstrate the efficacy of our approach on a wide range of applications and its value in exploring various design tradeoffs. I. MOTIVATIONThe relentless tracking of Moore's curve by the entire semiconductor industry has showcased the exponential scaling of the transistor feature size by a factor of 0.7 reduction every three years. This leads to exponentially increasing transistor counts and results in an explosive growth in functionality and the amount of computing power available on a single chip. Today it is perfectly feasible to design a System-on-a-Chip (SoC) with one billion transistors [7], and it is generally believed that industry will continue to overcome technical hurdles to sustain this trend for another decade. However, the cost of developing these chips and providing production facilities is also growing at a very fast pace. For instance, the total development cost of a single complex, high-density SoC at today's 90-nm technology can easily be in the $20 to $30 million range. The ITRS 2005 edition [7] has also emphasized that the cost of design remains the greatest threat to continuation of the semiconductor roadmap.Unfortunately, the progress of design technologies lags behind that of process manufacturing technologies. The constantly improving CAD tools can help to mitigate the problem by delivering faster simulation, higher capacity formal verification, and better logic synthesis coupled with place-androute. However, these improvements fail to close the design productivity gap, i.e., the number of available transistors grows faster than the ability to meaningfully design them.It is commonly acknowledged that the ultimate solution is to move to the next level of abstraction beyond RTL, and Electronic system-level (ESL) design automation has been widely identified as the next productivity boost for the semiconductor industry. However, despite some recent success in ESL simulation, the transition to ESL design will not be as well accepted as the transition to RTL without robust and efficient behavior-level and system-level syn...

Hardware acceleration is crucial in modern embedded system design to meet the explosive demands on performance and cost. Selected computation kernels for acceleration are usually captured by nest loops, which are optimized by state-of-the-art techniques like loop tiling and loop pipelining. However, memory bandwidth bottlenecks prevent designs to reach optimal throughput with respect to available parallelism. In this paper we present an automatic memory partitioning technique which can efficiently improve throughput and reduce energy consumption of pipelined loop kernels for given throughput constraints and platform requirement. Our partition scheme consists of two steps, the first step considers cycle accurate scheduling information to meet the hard constraints on memory bandwidth requirements specifically for synchronized hardware designs. Experimental results show an average 6X throughput improvement on a set of real world designs with moderate area increase (about 45% on average), given that less resource sharing opportunities exist with higher throughput in optimized designs. The second step further partitions the memory banks for reducing the dynamic power consumption of the final design. In contrast with previous approaches, our technique can statically compute memory access frequencies in polynomial time with little to none profiling. Experimental results show about 30% power reduction on the same set of benchmarks.