The realization of optical nonlinear activation functions (NAFs) is essential for integrated optical neural networks (ONNs). Here, we propose and experimentally demonstrate a photonic method to implement reconfigurable and low-threshold all-optical NAFs based on a compact and high-Q add-drop microring resonator (MRR) on silicon. In the experiment, four different NAFs including softplus, radial basis, clamped ReLU, and sigmoid functions are realized by exploiting the thermo-optical (TO) effect of the MRR. The threshold to implement NAFs is as low as 0.08 mW. As a demonstration, a handwritten digit classification benchmark task is simulated based on a convolutional neural network (CNN) using the obtained activation functions, where an accuracy of 98% is realized. Thanks to the unique advantages of ultra-compact footprint and ultralow threshold, the proposed nonlinear unit is promising to be widely used in large-scale integrated ONNs.

In recent years, notions drawn from non-Hermitian physics and parity-time (PT) symmetry have raised considerable attention in photonics, enabling various novel structures with entirely new and unexpected features. Here we propose, design, and optimize a compact passive PT-symmetric grating to achieve asymmetric reflection and diffraction based on a silicon-on-insulator (SOI) platform. The structure is composed of two sets of interleaved tailored gratings, which are all well-defined on the top of a silicon waveguide. Without additional loss or gain materials, the effective index and the scattering loss of the waveguide mode are modulated by the structure design. To our knowledge, it is the first time that the scattering loss arising from grating elements is regarded as an efficient way to realize PT-symmetric structure. The complicated multi-parameter optimization process of the proposed PT-symmetric grating is completed by using the particle swarm optimization (PSO) algorithm. In the simulation, asymmetric reflection with high contrast ratio is realized. We also find that the waveguide-to-free-space diffraction from one side of the structure is significantly suppressed, leading to asymmetric diffraction. Moreover, we investigate the fabrication tolerance of the proposed PT-symmetric grating. Our work provides a new perspective for exploring and creating complicated on-chip PT-symmetric devices.