The system in a package (SiP) including of a system on a chip (SoC) and a double-data-rate-three synchronous dynamic random access memory (DDR3 SDRAM) were studied with respect to the high-speed characteristics. The SiP was the multi-chip-module thin-profile fine-pitch ball grid array (MCM TFBGA) package with four-layer substrate. The high-speed 1600-Mbps data rate DDR3 signals were used in the signal integrity (SI) analysis. The SiP with low-cost silver (Ag) wires displayed a 500.18-ps aperture width in the eye diagram, which was successfully achieved signal integrity (SI) performance requirement. This work demonstrated the SiP with the Ag wires was the great potential solution for the advanced high-speed product applications.

GaAs power metal-semiconductor field-effect transistors (MESFETs) were fabricated using direct double silicon (Si) ion implantation technology for wireless communication applications. A 150-µm MESFET had a saturation drain current of 238 mA/mm after Si 3 N 4 passivation. A 15-mm MESFET, when measured under a class-AB condition with a biased drain voltage of 3.4 V and a quiescent drain current of 600 mA, delivered a maximum output power (P out ) of 31.1 dBm and a maximum power-added efficiency (PAE) of 58.0% at a frequency of 1.88 GHz. The MESFET exhibited a P out of 29.2 dBm with a PAE of 45.0% at the 1-dB gain compression point. The MESFET, when measured under a deep class-B condition with a biased drain voltage of 4.7 V and a quiescent drain current of 50 mA, achieved a maximum P out of 33.1 dBm and a maximum PAE of 55.9% at 1.88 GHz. The MESFET operating at 4.7 V and 1.88 GHz exhibited a P 1dB of 31.8 dBm and an associated PAE of 47.1% at the 1-dB gain compression point. When tested by IS-95 code-division multiple access (CDMA) standard signals and biased at 4.7 V under the deep class-B condition, the MESFET with a P out of 28 dBm demonstrated an adjacent channel power rejection (ACPR) of -31.2 dBc at +1.25 MHz apart from the 1.88 GHz center frequency and -45.7 dBc at +2.25 MHz.