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Micro bump interconnect with through-silicon via (TSV) is one of the critical issues for realizing three dimensional (3D) packages. This enabling technology provides more I/O in shrunken die area, and hence high density interconnection. Electroless Ni immersion Au (ENIG), electroless Ni electroless Pd immersion Au (ENEPIG), and plating Tin are commonly used surface finish for Cu pad in lead-free package. However, the majority of studies are focusing on Controlled Collapse Chip Connection (C4) solder. Intermetallic compounds (IMC) formation is a result of interaction between the solder tip, barrier layer, Cu pillar form the top die and micro pad finish from the interposer. As a result, microstructure made with different pad finish will major impact to solder reliability.In this study, three types of pad finish including ENIG, ENEPIG, and plating Tin were chosen to evaluate intermetallic formation during thermal cycling test. In addition, presence of Ni was also discussed to understand IMC formation in this microstructure. Multi reflow (at time zero, 1x, 3x) and thermal cycling test were performed for this evaluation. Metallurgy and growth kinetics of IMC were compared at different thermal cycling. The results show that SnAg bump with ENEPIG pad finish have more Cu consumption than ENIG after pre-con. ENEPIG pad finish exhibits crack formed between (Ni,Cu) 6 Sn 5 and P-rich layer. The detailed influence of Ni with various pad finish on the growth kinetics of IMC formation was investigated and discussed.

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Low-k dielectrics materials in the active layers on the chip surface has become a hot topic as most 90nm devices and all 65nm devices utilize low-k dielectrics materials. Low-k dielectrics materials provide a significant increase in performance of the devices but lowk materials have very low mechanical strength compared to the traditional dielectric films due to their porous nature, which results in low strength and poor adhesion qualities of the low-k dielectric materials. These lead to a unique set of mechanical issues when lowk die are packaged, the reliability of low-k flip chip packaging has become a critical issue. The coefficient of thermal expansion (CTE) mismatch between the silicon die and the substrate produces a bending or curvature of the assembly upon changes of temperature. This type of thermal/mechanical stress can lead to solder bump fatigue, delamination of the low-k dielectrics materials and the failure of the electronic package. Due to the mechanical sensitivity of the low-k material, stresses induced by the package has been demonstrated to exasperate the problem. Additionally, the tight bump pitch and low standoff height of future packages reduce the flow performance of conventional liquid capillary underfill (CUF) that results in low productivity (low unit per hour (UPH)) and low throughput. Thence, there is a need to use better technology to improve these problems, new molding underfill flip chip ball grid arrays (terminator FCBGA ® ) structure is developed. It uses hydrodynamic pressure of a mold press to transfer molten molding underfill material into the flip chip undergap, Therefore it does not have the same limitation as the conventional liquid capillary underfill (CUF) and the biggest advantage is its better coplanarity, high throughput , low stress , stronger bump protection, better solder joint capability and same thermal performance, especially for large package size and large die size. New molding underfill structure terminator FCBGA ® can provide strong bump protection and reach high reliability performance due to epoxy molding compound (EMC) low coefficient of thermal expansion (CTE) and high modulus. This kind of structure can also be applied all kind of bump composition such as tin-lead, high lead, and lead free. Furthermore, this paper also describes the process and reliability validation result.

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