A 512 x 512 monolithic PtSi Schottky Barrier Diode (SBD) array that was designed, fabricated and tested at EG &G Reticon will be discussed. The array uses a novel line-addressed charge -accumulation (LACA) CCD in an interline configuration for the vertical registers and a multiple-readout register for high speed readout. The LACA readout structure has two distinct advantages over the conventional interline CCD structure. First, the LACA register occupies a very small area while still providing enough charge handling capacity 'for the Schottky barrier detector. As a result, the 30.tm x 30 p.m pixels have a fill factor of 54% when designed with a 2.5 µm minimum dimension CCD process. Secondly, since the register operates in a charge accumulation mode, it has an extremely high effective charge accumulation efficiency. In the horizontal register, four readout structures are used to increase the overall pixel readout rate. A 75 Hz frame rate is achieved when the horizontal clock rate is 5 MHz. A CCD bending structure is utilized at each output to eliminate any coupling from the common clock lines. Each output has an electron sensitivity of greater than 5 .tV /e. The quantum yield of the platinum silicide SBDs has been between 15 and 25 %. The chip dimensions are 748 mil x 748 mil, of which 604 mil x 604 mil is photosensitive. ABSTRACTA 512 x 512 monolithic PtSi Schottky Barrier Diode (SBD) array that was designed, fabricated and tested at EG&G Reticon will be discussed. The array uses a novel line-addressed charge-accumulation (LACA) CCD in an interline configuration for the vertical registers and a multiple-readout register for high speed readout. The LACA readout structure has two distinct advantages over the conventional interline CCD structure. First, the LACA register occupies a very small area while still providing enough charge handling capacity »for the Schottky barrier detector. As a result, the 30 |im x 30 |im pixels have a fill factor of 54% when designed with a 2.5 Jim minimum dimension CCD process. Secondly, since the register operates in a charge accumulation mode, it has an extremely high effective charge accumulation efficiency. In the horizontal register, four readout structures are used to increase the overall pixel readout rate. A 75 Hz frame rate is achieved when the horizontal clock rate is 5 MHz. A CCD bending structure is utilized at each output to eliminate any coupling from the common clock lines. Each output has an electron sensitivity of greater than 5 jiV/e. The quantum yield of the platinum silicide SBDs has been between 15 and 25%. The chip dimensions are 748 mil x 748 mil, of which 604 mil x 604 mil is photosensitive.

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The Charge Coupled Device (CCD) has been widely used in full page scanner applications for many years. Since the length of a CCD is about one inch, a concave reduction lens is requred to focus the image ofa standard A4 size page of8.5 inches width on the CCD. This results in a bulky assembly. Moreover, the whole assembly needs to be moved by a high power stepping motor, which suffers from a non-smooth movement causing distortion in the image.A contact type image sensor (CIS) module is designed to solve the aforementioned problem. The dimensions of an A4 size CIS module is only 18 x 18 x 224 mm. The module has all the elements required to capture an image. These are: ( 1) a hybrid image sensor board (which consists ofa linear silicon butted image sensor array, an operational amplifier, and passive components); (2) an LED light source; (3) a one to one selfoc lens; (4) a cover glass and (5) an aluminum case to house all of the above components. The hybrid image sensor board is fabricated by butting many silicon image sensor chips end-to-end on top ofa ceramic substrate to achieve the desired length.Since the image sensor chip is silicon, the module can be operated at high clock rates with low noise characteristics. A resolution of200 and 400 dots per inch (dpi) are designed and developed for facsimile and scanner applications. The CIS device description, operation and performance will be presented in this paper.

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