No abstract

A tri-mode RF receiver with all digital automatic gain control (AGC) loop and non-uniform 2-bit analog-to-digital converter (ADC) is designed for the bands of GPS-L1, Galileo-E1 and Compass B1 in 0.18 lm CMOS process. The RF front-end, analog baseband and frequency synthesizer with voltage controlled oscillator (VCO) have been integrated, and there are only few offchip components including bypass capacitances, matching network and TCXO. For anti-jamming consideration, an all digital AGC loop with relevant variable gain amplifier (VGA) and non-uniform ADC is implemented to suppress interference and avoid saturation of signal chain. While drawing 35 mA current, this receiver achieves a total noise figure of 4 dB and a maximum gain of 105 dB, with a die area of 2.4 9 2.4 mm 2 .

In this paper, a 14-bit 100 MS/s pipelined Analog-to-Digital Converter (ADC) in 0.18 µm CMOS process with a SHA-less frontend is demonstrated. The methods of clock adjustment and voltage reference separation are proposed to speed up the settling of residue amplifier. Meanwhile, an effective digital background calibration mechanism is employed in the first two stages to correct both capacitor mismatches and linear gain error of residue amplifier. After calibration, the presented ADC achieves an spuriousfree dynamic range (SFDR) of 89 dB, a signal-to-noise ratio (SNR) of 74.5 dB and a signal-to-noise and distortion ratio (SNDR) of 74.2 dB with a 30.2 MHz input signal, while keeping over 71.6 dB SNR and 70.2 dB SFDR with input signals up to 200 MHz. The chip consumes 440 mW from a 1.8 V supply and occupies an area of 4 × 2.6 mm 2 .

A dual-mode complementary metal-oxide-semiconductor (CMOS) receiver operating from 1 to 2 GHz is presented. The proposed receiver employs a switchable low-noise amplifier (LNA) and two separated down-conversion paths to realise dual-mode operation. For receiving weak signals without large blockers, the receiver works in the high-gain mode which adopts the common gate (CG)-common source (CS) LNA and the active-mixer-based down-conversion path to achieve high gain and low noise figure (NF). In the case of large in-band blockers, the receiver works in the high linearity mode, which uses the LNA as a low-noise transimpedance amplifier followed by a 25% duty-cycle current-driving passive mixer and a transimpedance amplifier based on current buffer to obtain high in-band linearity. Implemented in a 0.18 μmC M O S technology, this receiver achieves 4.9 dB NF and a voltage gain range of 29.4-92.6 dB in high-gain mode, whereas +0.9 dBm in-band input-referred third-order interception and a voltage gain range of 15.8-20.1 dB in high linearity mode.

No abstract