We present a gate sizing tool using a posynomial delay model. The resulting optimization problem is a Geometric Program (GP) and is efficiently solved using Matlab toolbox GGPLAB. The effectiveness of our gate sizing is demonstrated by applying the optimization on the ISCAS'85 benchmark circuits compared with the sizes found in a typical commercial cell library. Experimental results show that the speed is increased by 21%, in average, for the circuits using the gates sized with our gate sizer, and power consumption and area are maintained. Using the automatic cell generation tool ASTRAN, we can generate the cells in the desired size and take advantage of having cells scaled to the optimal or near optimal size.