The shortage of graduates in Science, Technology, Engineering and Mathematics (STEM), has led to numerous attempts to increase students' interest in STEM. One emerging approach that has the potential to improve students' motivation for STEM is integrated STEM education. Nonetheless, the implementation of this new instructional strategy is not straightforward due to the lack of consensus about instructional practices in integrated STEM. This paper contributes to this challenge by providing a well-defined framework for instructional practices in integrated STEM in secondary education, based on the results of a systematic review of existing literature. The framework contains five key principles: integration of STEM content, problem-centered learning, inquiry-based learning, design-based learning and cooperative learning. The proposed framework has several benefits, including its applicability in the classroom and the possibility to describe integrated STEM on multiple dimensions. Nonetheless, further research is necessary to investigate the effects of integrated STEM on students' cognitive and affective learning outcomes.

No abstract

SRAM cell read stability and write-ability are major concerns in nanometer CMOS technologies, due to the progressive increase in intra-die variability and scaling. This paper analyzes the read stability N-curve metrics and compares them with the commonly used static noise margin (SNM) metric defined by Seevinck. Additionally, new write-ability metrics derived from the same N-curve are introduced and compared with the traditional write-trip point definition. Analytical models of all these metrics are developed. It is demonstrated that the new metrics provide additional information in terms of current, which allows designing a more robust and stable cell. By taking into account this current information, scaling is no longer a limiting factor for the read stability of the cell. Finally, these metrics are used to investigate the impact of the intra-die variability on the stability of the cell by using a statistically-aware circuit optimization approach and the results are compared with the worst-case or corner-based design.

ConvNets, or Convolutional Neural Networks (CNN), are state-of-the-art classification algorithms, achieving near-human performance in visual recognition [1]. New trends such as augmented reality demand always-on visual processing in wearable devices. Yet, advanced ConvNets achieving high recognition rates are too expensive in terms of energy as they require substantial data movement and billions of convolution computations. Today, state-of-the-art mobile GPU's and ConvNet accelerator ASICs [2][3] only demonstrate energy-efficiencies of 10's to several 100's GOPS/W, which is one order of magnitude below requirements for always-on applications. This paper introduces the concept of hierarchical recognition processing, combined with the Envision platform: an energy-scalable ConvNet processor achieving efficiencies up to 10TOPS/W, while maintaining recognition rate and throughput. Envision hereby enables always-on visual recognition in wearable devices. Figure 14.5.1 demonstrates the concept of hierarchical recognition. Here, a hierarchy of increasingly complex individually trained ConvNets, with different topologies, different network sizes and increasing computational precision requirements, is used in the context of person identification. This enables constant scanning for faces at very low average energy cost, yet rapidly scales up to more complex networks detecting a specific face such as a device's owner, all the way up to full VGG-16-based 5760-face recognition. The opportunities afforded by such a hierarchical approach span far beyond face recognition alone, but can only be exploited by digital systems demonstrating wide-range energy scalability across computational precision. State-of-the-art ASICs in references [3] and [4] only show 1.5× and 8.2× energy-efficiency scalability, respectively. Envision improves upon this by introducing subword-parallel Dynamic-Voltage-AccuracyFrequency Scaling (DVAFS), a circuit-level technique enabling 40× energy-precision scalability at constant throughput. Figure 14.5.2 illustrates the basic principle of DVAFS and compares it to Dynamic-Accuracy Scaling (DAS) and Dynamic-Voltage-Accuracy Scaling (DVAS) [4]. In DAS, switching activity and hence energy consumption is reduced for low precision computations by rounding and masking a configurable number of LSB's at the inputs of multiplyaccumulate (MAC) units. DVAS exploits shorter critical paths in DAS's reduced-precision modes by combining it with voltage scaling for increased energy scalability. This paper proposes subword-parallel DVAFS, which further improves upon DVAS, by reusing inactive arithmetic cells at reduced precision. These can be reconfigured to compute 2×1-8b or 4×1-4b (N×1-16b/N, with N the level of subword-parallelism), rather than 1×1-16b words per cycle, when operating at less than 8b precision. At constant data throughput, this permits lowering the processor's frequency and voltage significantly below DVAS values. As a result, DVAFS is a dynamic precision technique which simultaneously lowers all run-time a...